TY - GEN
T1 - Test planning for mixed-signal SOCs with wrapped analog cores
AU - Sehgal, Anuja
AU - Liu, Fang
AU - Ozev, Sule
AU - Chakrabarty, Krishnendu
PY - 2005
Y1 - 2005
N2 - Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented, heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transi star-level simulations for an analog wrapper and a representative core. We present experimental results on test scheduling for an ITC'02 benchmark SOC that has been augmented with five analog cores.
AB - Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented, heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transi star-level simulations for an analog wrapper and a representative core. We present experimental results on test scheduling for an ITC'02 benchmark SOC that has been augmented with five analog cores.
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U2 - 10.1109/DATE.2005.303
DO - 10.1109/DATE.2005.303
M3 - Conference contribution
AN - SCOPUS:33646919808
SN - 0769522882
SN - 9780769522883
T3 - Proceedings -Design, Automation and Test in Europe, DATE '05
SP - 50
EP - 55
BT - Proceedings - Design, Automation and Test in Europe, DATE '05
T2 - Design, Automation and Test in Europe, DATE '05
Y2 - 7 March 2005 through 11 March 2005
ER -