TY - GEN
T1 - Test yield estimation for analog/RF circuits over multiple correlated measurements
AU - Fang, Liu
AU - Acar, Erkan
AU - Ozev, Sule
N1 - Funding Information:
* This research was supported by NIMH Research Scientist Award 14120. Project Grant MH-22916. and General Research Support grants 27-1989 and 27-1921 from Rutgers Medical School to the first author. We are grateful to Dr. Schmale for making available the transcripts of the interviews analyzed in this stud!. We wish to thank Howard Zager for computer programming assist-ance. Caryn Dickman for keypunching of transcripts and management of data processing. and Dale Hahn and Doroth! Gioia for the defendedness ratings.
PY - 2008
Y1 - 2008
N2 - Circuit and test yield information provides essential feedback to circuit designers and test engineers to evaluate their designs and test set-ups. Traditionally, Monte Carlo analysis and other sample-and-simulate based approaches have been used for yield estimation. However, such computationally costly techniques cannot be used if yield estimation needs to be repeated multiple times, as in the case of test evaluation. In this paper, we propose a technique to conduct accurate and efficient overall yield estimation based on hybrid quadratic modelling and hierarchical statistical profiling. We also develop compatible models for environmental noise and measurement error, two most important error sources in the test process. Our experiments on a baseband amplifier and a cascaded LNA-mixer circuit confirm that the proposed yield estimation technique achieves significant computational time saving with negligible accuracy loss when used for multiple test set-up evaluations.
AB - Circuit and test yield information provides essential feedback to circuit designers and test engineers to evaluate their designs and test set-ups. Traditionally, Monte Carlo analysis and other sample-and-simulate based approaches have been used for yield estimation. However, such computationally costly techniques cannot be used if yield estimation needs to be repeated multiple times, as in the case of test evaluation. In this paper, we propose a technique to conduct accurate and efficient overall yield estimation based on hybrid quadratic modelling and hierarchical statistical profiling. We also develop compatible models for environmental noise and measurement error, two most important error sources in the test process. Our experiments on a baseband amplifier and a cascaded LNA-mixer circuit confirm that the proposed yield estimation technique achieves significant computational time saving with negligible accuracy loss when used for multiple test set-up evaluations.
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U2 - 10.1109/TEST.2007.4437643
DO - 10.1109/TEST.2007.4437643
M3 - Conference contribution
AN - SCOPUS:39749199576
SN - 1424411289
SN - 9781424411283
T3 - Proceedings - International Test Conference
BT - 2007 IEEE International Test Conference, ITC
T2 - 2007 IEEE International Test Conference, ITC
Y2 - 23 October 2007 through 25 October 2007
ER -