Test yield estimation for analog/RF circuits over multiple correlated measurements

Liu Fang, Erkan Acar, Sule Ozev

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Circuit and test yield information provides essential feedback to circuit designers and test engineers to evaluate their designs and test set-ups. Traditionally, Monte Carlo analysis and other sample-and-simulate based approaches have been used for yield estimation. However, such computationally costly techniques cannot be used if yield estimation needs to be repeated multiple times, as in the case of test evaluation. In this paper, we propose a technique to conduct accurate and efficient overall yield estimation based on hybrid quadratic modelling and hierarchical statistical profiling. We also develop compatible models for environmental noise and measurement error, two most important error sources in the test process. Our experiments on a baseband amplifier and a cascaded LNA-mixer circuit confirm that the proposed yield estimation technique achieves significant computational time saving with negligible accuracy loss when used for multiple test set-up evaluations.

Original languageEnglish (US)
Title of host publication2007 IEEE International Test Conference, ITC
StatePublished - 2008
Externally publishedYes
Event2007 IEEE International Test Conference, ITC - Santa Clara, CA, United States
Duration: Oct 23 2007Oct 25 2007

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539


Other2007 IEEE International Test Conference, ITC
Country/TerritoryUnited States
CitySanta Clara, CA

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics


Dive into the research topics of 'Test yield estimation for analog/RF circuits over multiple correlated measurements'. Together they form a unique fingerprint.

Cite this