Single-Event Gate Rupture Hardened Structure for High-Voltage Super-Junction Power MOSFETs

K. Muthuseenu; H. J. Barnaby; K. F. Galloway; A. E. Koziukov; T. A. Maksimenko; M. Y. Vyrostkov; K. B. Bu-Khasan; A. A. Kalashnikova; A. Privat

doi:10.1109/TED.2021.3091952

Single-Event Gate Rupture Hardened Structure for High-Voltage Super-Junction Power MOSFETs

K. Muthuseenu, H. J. Barnaby, K. F. Galloway, A. E. Koziukov, T. A. Maksimenko, M. Y. Vyrostkov, K. B. Bu-Khasan, A. A. Kalashnikova, A. Privat

Research output: Contribution to journal › Article › peer-review

10 Scopus citations

Abstract

This article presents design for a 650-V super-junction (SJ) power metal-oxide-semiconductor field effect transistor (MOSFET) which improves tolerance to both single-event burnout (SEB) and single-event gate rupture (SEGR). Experimental measurements of SEGR in a generic commercial planar gate SJ device are used to validate the accuracy of the design. In an SJ device with a planar gate, reducing the neck width improves the tolerance to gate rupture but significantly changes the electrical device characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P+-plug are added to the trench gate SJ power transistor to improve SEB tolerance. The proposed trench gate structure improves the SEGR survivability by a factor of 10.

Original language	English (US)
Article number	9477631
Pages (from-to)	4004-4009
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	68
Issue number	8
DOIs	https://doi.org/10.1109/TED.2021.3091952
State	Published - Aug 2021

Keywords

Heavy ion
power metal-oxide-semiconductor field effect transistor (MOSFET)
single-event burnout (SEB)
single-event effect (SEE)
single-event gate rupture (SEGR)
single-event hardening
super-junction (SJ)
technology computer-aided design (TCAD) simulation

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/TED.2021.3091952

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title = "Single-Event Gate Rupture Hardened Structure for High-Voltage Super-Junction Power MOSFETs",

abstract = "This article presents design for a 650-V super-junction (SJ) power metal-oxide-semiconductor field effect transistor (MOSFET) which improves tolerance to both single-event burnout (SEB) and single-event gate rupture (SEGR). Experimental measurements of SEGR in a generic commercial planar gate SJ device are used to validate the accuracy of the design. In an SJ device with a planar gate, reducing the neck width improves the tolerance to gate rupture but significantly changes the electrical device characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P+-plug are added to the trench gate SJ power transistor to improve SEB tolerance. The proposed trench gate structure improves the SEGR survivability by a factor of 10.",

keywords = "Heavy ion, power metal-oxide-semiconductor field effect transistor (MOSFET), single-event burnout (SEB), single-event effect (SEE), single-event gate rupture (SEGR), single-event hardening, super-junction (SJ), technology computer-aided design (TCAD) simulation",

author = "K. Muthuseenu and Barnaby, {H. J.} and Galloway, {K. F.} and Koziukov, {A. E.} and Maksimenko, {T. A.} and Vyrostkov, {M. Y.} and Bu-Khasan, {K. B.} and Kalashnikova, {A. A.} and A. Privat",

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year = "2021",

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language = "English (US)",

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AU - Muthuseenu, K.

AU - Barnaby, H. J.

AU - Galloway, K. F.

AU - Koziukov, A. E.

AU - Maksimenko, T. A.

AU - Vyrostkov, M. Y.

AU - Bu-Khasan, K. B.

AU - Kalashnikova, A. A.

AU - Privat, A.

PY - 2021/8

Y1 - 2021/8

N2 - This article presents design for a 650-V super-junction (SJ) power metal-oxide-semiconductor field effect transistor (MOSFET) which improves tolerance to both single-event burnout (SEB) and single-event gate rupture (SEGR). Experimental measurements of SEGR in a generic commercial planar gate SJ device are used to validate the accuracy of the design. In an SJ device with a planar gate, reducing the neck width improves the tolerance to gate rupture but significantly changes the electrical device characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P+-plug are added to the trench gate SJ power transistor to improve SEB tolerance. The proposed trench gate structure improves the SEGR survivability by a factor of 10.

AB - This article presents design for a 650-V super-junction (SJ) power metal-oxide-semiconductor field effect transistor (MOSFET) which improves tolerance to both single-event burnout (SEB) and single-event gate rupture (SEGR). Experimental measurements of SEGR in a generic commercial planar gate SJ device are used to validate the accuracy of the design. In an SJ device with a planar gate, reducing the neck width improves the tolerance to gate rupture but significantly changes the electrical device characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P+-plug are added to the trench gate SJ power transistor to improve SEB tolerance. The proposed trench gate structure improves the SEGR survivability by a factor of 10.

KW - Heavy ion

KW - power metal-oxide-semiconductor field effect transistor (MOSFET)

KW - single-event burnout (SEB)

KW - single-event effect (SEE)

KW - single-event gate rupture (SEGR)

KW - single-event hardening

KW - super-junction (SJ)

KW - technology computer-aided design (TCAD) simulation

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ER -

Single-Event Gate Rupture Hardened Structure for High-Voltage Super-Junction Power MOSFETs

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Keywords

ASJC Scopus subject areas

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