Single-Event Gate Rupture Hardened Structure for High-Voltage Super-Junction Power MOSFETs

K. Muthuseenu, H. J. Barnaby, K. F. Galloway, A. E. Koziukov, T. A. Maksimenko, M. Y. Vyrostkov, K. B. Bu-Khasan, A. A. Kalashnikova, A. Privat

Research output: Contribution to journalArticlepeer-review

7 Scopus citations


This article presents design for a 650-V super-junction (SJ) power metal-oxide-semiconductor field effect transistor (MOSFET) which improves tolerance to both single-event burnout (SEB) and single-event gate rupture (SEGR). Experimental measurements of SEGR in a generic commercial planar gate SJ device are used to validate the accuracy of the design. In an SJ device with a planar gate, reducing the neck width improves the tolerance to gate rupture but significantly changes the electrical device characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P+-plug are added to the trench gate SJ power transistor to improve SEB tolerance. The proposed trench gate structure improves the SEGR survivability by a factor of 10.

Original languageEnglish (US)
Article number9477631
Pages (from-to)4004-4009
Number of pages6
JournalIEEE Transactions on Electron Devices
Issue number8
StatePublished - Aug 2021


  • Heavy ion
  • power metal-oxide-semiconductor field effect transistor (MOSFET)
  • single-event burnout (SEB)
  • single-event effect (SEE)
  • single-event gate rupture (SEGR)
  • single-event hardening
  • super-junction (SJ)
  • technology computer-aided design (TCAD) simulation

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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