Parametric fault diagnosis for analog circuits using a Bayesian framework

Fang Liu, Plamen K. Nikolov, Sule Ozev

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Scopus citations


In this paper, we present a parametric fault diagnosis approach for analog/RF circuits based on a Bayesian framework. The Bayesian fault diagnosis requires extensive statistical profiling which is enabled by a an efficient hierarchical process variability analysis. Both DC and AC parameters are used as measurements to provide maximum diagnostic resolution. A sensitivity guided test input selection scheme is used to determine the measurement attributes that are most likely to distinguish among the faults. Fault dictionaries are constructed using parametric faults at the transistor level that have both marginal and higher deviations. During the diagnosis step, additional online profiling helps increase the diagnostic resolution. Experiments on a transistor level amplifier circuit confirms that the approach is accurate in terms of statistical attributes and most deviations in layout and process level parameters can be correctly diagnosed.

Original languageEnglish (US)
Title of host publicationProceedings - 24th IEEE VLSI Test Symposium
Number of pages6
StatePublished - Nov 22 2006
Externally publishedYes
Event24th IEEE VLSI Test Symposium - Berkeley, CA, United States
Duration: Apr 30 2006May 4 2006

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Other24th IEEE VLSI Test Symposium
Country/TerritoryUnited States
CityBerkeley, CA

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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