TY - GEN
T1 - Online information utility assessment for per-device adaptive test flow
AU - Li, Yanjun
AU - Yilmaz, Ender
AU - Sarson, Peter
AU - Ozev, Sule
N1 - Funding Information:
1 Project NO. ZYGX2016J220 Supported by Fundamental Research Funds for the Central Universities, China.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/5/29
Y1 - 2018/5/29
N2 - Per-device adaptive test is a promising direction with the best trade-off between test quality and test time so far. In this work, we propose a method for online assessment of the information content of the next test in the test queue. This assessment can be used to tune the trade-off between test quality and test time of a per-device adaptive test. Since majority of specification parameters are correlated, the overall information content of multiple tests is difficult to extract. We model multi-variate correlations among specification parameters and take these correlations into account to estimate the multivariate overall information utility of a given set of tests. The proposed method can be integrated within an existing adaptive test flow (per-device or per-wafer) that runs in the background. Experimental results using 3 distinct industry circuits and sizable data show that the proposed technique can finely tune the trade-off, even achieve zero test escape rates with appreciable test time savings.
AB - Per-device adaptive test is a promising direction with the best trade-off between test quality and test time so far. In this work, we propose a method for online assessment of the information content of the next test in the test queue. This assessment can be used to tune the trade-off between test quality and test time of a per-device adaptive test. Since majority of specification parameters are correlated, the overall information content of multiple tests is difficult to extract. We model multi-variate correlations among specification parameters and take these correlations into account to estimate the multivariate overall information utility of a given set of tests. The proposed method can be integrated within an existing adaptive test flow (per-device or per-wafer) that runs in the background. Experimental results using 3 distinct industry circuits and sizable data show that the proposed technique can finely tune the trade-off, even achieve zero test escape rates with appreciable test time savings.
UR - http://www.scopus.com/inward/record.url?scp=85048356488&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85048356488&partnerID=8YFLogxK
U2 - 10.1109/VTS.2018.8368662
DO - 10.1109/VTS.2018.8368662
M3 - Conference contribution
AN - SCOPUS:85048356488
T3 - Proceedings of the IEEE VLSI Test Symposium
SP - 1
EP - 6
BT - Proceedings - 2018 IEEE 36th VLSI Test Symposium, VTS 2018
PB - IEEE Computer Society
T2 - 36th IEEE VLSI Test Symposium, VTS 2018
Y2 - 22 April 2018 through 25 April 2018
ER -