Interlayer Engineering to Achieve <1 m2K/GW Thermal Boundary Resistances to Diamond for Effective Device Cooling

K. Woo; M. Malakoutian; Y. Jo; X. Zheng; T. Pfeifer; R. Mandia; T. Hwang; H. Aller; D. Field; A. Kasperovich; D. Saraswat; D. Smith; P. Hopkins; S. Graham; M. Kuball; K. Cho; Srabanti Chowdhury

doi:10.1109/IEDM45741.2023.10413734

Interlayer Engineering to Achieve <1 m²K/GW Thermal Boundary Resistances to Diamond for Effective Device Cooling

K. Woo, M. Malakoutian, Y. Jo, X. Zheng, T. Pfeifer, R. Mandia, T. Hwang, H. Aller, D. Field, A. Kasperovich, D. Saraswat, D. Smith, P. Hopkins, S. Graham, M. Kuball, K. Cho, Srabanti Chowdhury

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

Highly localized electric fields and resulting high-temperature spots can cause channel performance degradation in semiconductor devices, which eventually leads to premature failure due to thermal runaway. To address these challenges, well-designed thermal management at the device/chip level is crucial. Diamond due to its high thermal conductivity is an effective heat-spreader when integrated near the hot spot in the channel/junction. However, a significant bottleneck lies in the thermal boundary resistance (TBR) between the hot spot generated in the device and the heat spreader. Here, atomistic thermal transport modeling was first used to show the reduction of TBR below the diffuse-mismatch (DMM) theory predictions is possible with a thin SiC interlayer. Then, experimentally, the SiC interlayer crystallinity and thickness were engineered to produce TBRs of 3.1±0.7 and 1.89±0.18 m²K/GW. TBRs in this range, alone can lead to W-band power to > 30 W/mm in GaN HEMTs. Such low TBR would lead to greater reliability and performance for both GaN and Si technologies.

Original language	English (US)
Title of host publication	2023 International Electron Devices Meeting, IEDM 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350327670
DOIs	https://doi.org/10.1109/IEDM45741.2023.10413734
State	Published - 2023
Externally published	Yes
Event	2023 International Electron Devices Meeting, IEDM 2023 - San Francisco, United States Duration: Dec 9 2023 → Dec 13 2023

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Conference

Conference	2023 International Electron Devices Meeting, IEDM 2023
Country/Territory	United States
City	San Francisco
Period	12/9/23 → 12/13/23

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Access to Document

10.1109/IEDM45741.2023.10413734

Cite this

Woo, K., Malakoutian, M., Jo, Y., Zheng, X., Pfeifer, T., Mandia, R., Hwang, T., Aller, H., Field, D., Kasperovich, A., Saraswat, D., Smith, D., Hopkins, P., Graham, S., Kuball, M., Cho, K., & Chowdhury, S. (2023). Interlayer Engineering to Achieve <1 m²K/GW Thermal Boundary Resistances to Diamond for Effective Device Cooling. In 2023 International Electron Devices Meeting, IEDM 2023 (Technical Digest - International Electron Devices Meeting, IEDM). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM45741.2023.10413734

Interlayer Engineering to Achieve <1 m²K/GW Thermal Boundary Resistances to Diamond for Effective Device Cooling. / Woo, K.; Malakoutian, M.; Jo, Y. et al.
2023 International Electron Devices Meeting, IEDM 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Woo, K, Malakoutian, M, Jo, Y, Zheng, X, Pfeifer, T, Mandia, R, Hwang, T, Aller, H, Field, D, Kasperovich, A, Saraswat, D, Smith, D, Hopkins, P, Graham, S, Kuball, M, Cho, K & Chowdhury, S 2023, Interlayer Engineering to Achieve <1 m²K/GW Thermal Boundary Resistances to Diamond for Effective Device Cooling. in 2023 International Electron Devices Meeting, IEDM 2023. Technical Digest - International Electron Devices Meeting, IEDM, Institute of Electrical and Electronics Engineers Inc., 2023 International Electron Devices Meeting, IEDM 2023, San Francisco, United States, 12/9/23. https://doi.org/10.1109/IEDM45741.2023.10413734

Woo K, Malakoutian M, Jo Y, Zheng X, Pfeifer T, Mandia R et al. Interlayer Engineering to Achieve <1 m²K/GW Thermal Boundary Resistances to Diamond for Effective Device Cooling. In 2023 International Electron Devices Meeting, IEDM 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM45741.2023.10413734

@inproceedings{f86410d3f33e48e0b8d767f8c9652d93,

title = "Interlayer Engineering to Achieve <1 m2K/GW Thermal Boundary Resistances to Diamond for Effective Device Cooling",

abstract = "Highly localized electric fields and resulting high-temperature spots can cause channel performance degradation in semiconductor devices, which eventually leads to premature failure due to thermal runaway. To address these challenges, well-designed thermal management at the device/chip level is crucial. Diamond due to its high thermal conductivity is an effective heat-spreader when integrated near the hot spot in the channel/junction. However, a significant bottleneck lies in the thermal boundary resistance (TBR) between the hot spot generated in the device and the heat spreader. Here, atomistic thermal transport modeling was first used to show the reduction of TBR below the diffuse-mismatch (DMM) theory predictions is possible with a thin SiC interlayer. Then, experimentally, the SiC interlayer crystallinity and thickness were engineered to produce TBRs of 3.1±0.7 and 1.89±0.18 m2K/GW. TBRs in this range, alone can lead to W-band power to > 30 W/mm in GaN HEMTs. Such low TBR would lead to greater reliability and performance for both GaN and Si technologies.",

author = "K. Woo and M. Malakoutian and Y. Jo and X. Zheng and T. Pfeifer and R. Mandia and T. Hwang and H. Aller and D. Field and A. Kasperovich and D. Saraswat and D. Smith and P. Hopkins and S. Graham and M. Kuball and K. Cho and Srabanti Chowdhury",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 2023 International Electron Devices Meeting, IEDM 2023 ; Conference date: 09-12-2023 Through 13-12-2023",

year = "2023",

doi = "10.1109/IEDM45741.2023.10413734",

language = "English (US)",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2023 International Electron Devices Meeting, IEDM 2023",

}

TY - GEN

T1 - Interlayer Engineering to Achieve <1 m2K/GW Thermal Boundary Resistances to Diamond for Effective Device Cooling

AU - Woo, K.

AU - Malakoutian, M.

AU - Jo, Y.

AU - Zheng, X.

AU - Pfeifer, T.

AU - Mandia, R.

AU - Hwang, T.

AU - Aller, H.

AU - Field, D.

AU - Kasperovich, A.

AU - Saraswat, D.

AU - Smith, D.

AU - Hopkins, P.

AU - Graham, S.

AU - Kuball, M.

AU - Cho, K.

AU - Chowdhury, Srabanti

PY - 2023

Y1 - 2023

N2 - Highly localized electric fields and resulting high-temperature spots can cause channel performance degradation in semiconductor devices, which eventually leads to premature failure due to thermal runaway. To address these challenges, well-designed thermal management at the device/chip level is crucial. Diamond due to its high thermal conductivity is an effective heat-spreader when integrated near the hot spot in the channel/junction. However, a significant bottleneck lies in the thermal boundary resistance (TBR) between the hot spot generated in the device and the heat spreader. Here, atomistic thermal transport modeling was first used to show the reduction of TBR below the diffuse-mismatch (DMM) theory predictions is possible with a thin SiC interlayer. Then, experimentally, the SiC interlayer crystallinity and thickness were engineered to produce TBRs of 3.1±0.7 and 1.89±0.18 m2K/GW. TBRs in this range, alone can lead to W-band power to > 30 W/mm in GaN HEMTs. Such low TBR would lead to greater reliability and performance for both GaN and Si technologies.

AB - Highly localized electric fields and resulting high-temperature spots can cause channel performance degradation in semiconductor devices, which eventually leads to premature failure due to thermal runaway. To address these challenges, well-designed thermal management at the device/chip level is crucial. Diamond due to its high thermal conductivity is an effective heat-spreader when integrated near the hot spot in the channel/junction. However, a significant bottleneck lies in the thermal boundary resistance (TBR) between the hot spot generated in the device and the heat spreader. Here, atomistic thermal transport modeling was first used to show the reduction of TBR below the diffuse-mismatch (DMM) theory predictions is possible with a thin SiC interlayer. Then, experimentally, the SiC interlayer crystallinity and thickness were engineered to produce TBRs of 3.1±0.7 and 1.89±0.18 m2K/GW. TBRs in this range, alone can lead to W-band power to > 30 W/mm in GaN HEMTs. Such low TBR would lead to greater reliability and performance for both GaN and Si technologies.

UR - http://www.scopus.com/inward/record.url?scp=85185605519&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85185605519&partnerID=8YFLogxK

U2 - 10.1109/IEDM45741.2023.10413734

DO - 10.1109/IEDM45741.2023.10413734

M3 - Conference contribution

AN - SCOPUS:85185605519

T3 - Technical Digest - International Electron Devices Meeting, IEDM

BT - 2023 International Electron Devices Meeting, IEDM 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2023 International Electron Devices Meeting, IEDM 2023

Y2 - 9 December 2023 through 13 December 2023

ER -