Fault-based Built-in Self-test and Evaluation of Phase Locked Loops

Mehmet Ince, Ender Yilmaz, Wei Fu, Joonsung Park, Krishnaswamy Nagaraj, Leroy Winemberg, Sule Ozev

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This article presents a very low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65 nm technology. Fault simulations performed at the transistor and system-level show that the majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.

Original languageEnglish (US)
Article number20
JournalACM Transactions on Design Automation of Electronic Systems
Issue number3
StatePublished - Feb 2021


  • Mixed signal circuit testing
  • built-in self test
  • phase locked loops
  • pseudo random binary sequence

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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