TY - GEN
T1 - End-to-end testability analysis and DfT insertion for mixed-signal paths
AU - Ozev, Sule
AU - Orailoglu, Alex
PY - 2004/12/1
Y1 - 2004/12/1
N2 - Increasing system complexity and test cost demands new system-level solutions for mixed-signal systems. In this paper, we present a testability analysis and DfT insertion methodology for end-to-end mixed-signal paths. Based on behavioral models and path analysis, testability problems in the path are determined and classified in terms of their bottleneck. Possible solutions to each problem are identified. The DfT insertion problem is then formulated as a min-cost set cover problem to achieve the most cost-efficient solution. In experimental results where test point insertion is used as the DfT approach, nearly 50% reduction in the overall DfT overhead is achieved.
AB - Increasing system complexity and test cost demands new system-level solutions for mixed-signal systems. In this paper, we present a testability analysis and DfT insertion methodology for end-to-end mixed-signal paths. Based on behavioral models and path analysis, testability problems in the path are determined and classified in terms of their bottleneck. Possible solutions to each problem are identified. The DfT insertion problem is then formulated as a min-cost set cover problem to achieve the most cost-efficient solution. In experimental results where test point insertion is used as the DfT approach, nearly 50% reduction in the overall DfT overhead is achieved.
UR - http://www.scopus.com/inward/record.url?scp=17644421525&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=17644421525&partnerID=8YFLogxK
U2 - 10.1109/ICCD.2004.1347902
DO - 10.1109/ICCD.2004.1347902
M3 - Conference contribution
AN - SCOPUS:17644421525
SN - 0769522319
T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
SP - 72
EP - 77
BT - Proceedings - IEEE International Conference on Computer Design
T2 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004
Y2 - 11 October 2004 through 13 October 2004
ER -