Enabling fast process variation and fault simulation through macromodelling of analog components

Mehmet Ince, Ender Yilmaz, Sule Ozev

Research output: Chapter in Book/Report/Conference proceedingConference contribution


With the advent of built-in self-test (BIST) in analog and RF circuits, it is essential that the fault coverage of potential BIST solutions be evaluated before they are deployed. However, large scale fault simulations are often infeasible even when considering the extensive computational power available today. Fault simulations are more challenging for devices that contain frequency transformation, such as phased locked loops (PLLs) or mixers. Thus, a mixed-mode simulation is necessary that captures fault behavior at the lower levels of the hierarchy and propagates this information to the system-level. Mixed-mode simulators, such as Verilog-A, can be used for evaluating nominal circuit behavior but falls short when evaluating faulty circuit behavior. This paper presents a macro modeling approach for mixed-signal circuits through a case study of voltage controlled oscillators (VCOs) used in PLLs. The evaluated BIST technique is the measurement of the phase transfer function from the input to the output. This requires a long transient simulation due to the need to capture the high frequency behavior of the PLL while covering the settling time of the low-frequency filter and VCO input. As the ratio of the output to the input frequency increases, simulation time also increases, making the analyses prohibitively expensive for some cases. In this paper, we build a MATLAB/Simulink model of the VCO and PLL, which is also designed and simulated at the transistor level using the FinFET technology. By modeling free running frequency, sensitivity, duty cycle, non-linearity, and phase noise characteristic of the VCO, we show that both PLL simulations, one using Spice, and one using the proposed macromodeling technique along with Simulink, match in response whereas the proposed approach only takes a fraction of time of Spice simulations.

Original languageEnglish (US)
Title of host publication27th North Atlantic Test Workshop, NATW 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Electronic)9781538664001
StatePublished - Jun 19 2018
Event27th North Atlantic Test Workshop, NATW 2018 - Essex, United States
Duration: May 7 2018May 9 2018

Publication series

Name27th North Atlantic Test Workshop, NATW 2018


Other27th North Atlantic Test Workshop, NATW 2018
Country/TerritoryUnited States

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Modeling and Simulation
  • Safety, Risk, Reliability and Quality


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