TY - GEN
T1 - Development and empirical verification of an accuracy model for the power down leakage tests
AU - Jeong, Jae Woong
AU - Ozev, Sule
AU - Taenzler, Friedrich
AU - Chao, Hui Chuan
PY - 2014
Y1 - 2014
N2 - Power down leakage (PDL) test is one of the most sensitive tests to verify device integrity during production test. Generally, the PDL current is measured once at the beginning and once at the end of the production test cycle in order to verify that the test process has not degraded device integrity. This current measurement is typically repeated 100 times or more to achieve accurate results. A wide variation in the measurement results usually necessitates additional measurements and averaging. However, without the proper modeling and analysis, repeating the measurement and averaging results alone will not guarantee the accuracy. In this paper, we analyze root causes of the error for the PDL current measurements. Our analysis indicates that while quantization error and thermal noise have negligible impact on the error of the measurements, the instrument accuracy, timing, and temperature based variation are the major contributors to accuracy. We develop a new accuracy model for the PDL current measurement to account for these major contributors. Using this model, we propose a new systematic optimization method for the test process to achieve the desired accuracy without increasing the test time unreasonably. This method and the model are empirically verified with hardware experiments. With hardware experiments we also show that we can reduce the test time nearly 3-fold using the optimized test sequencing strategy.
AB - Power down leakage (PDL) test is one of the most sensitive tests to verify device integrity during production test. Generally, the PDL current is measured once at the beginning and once at the end of the production test cycle in order to verify that the test process has not degraded device integrity. This current measurement is typically repeated 100 times or more to achieve accurate results. A wide variation in the measurement results usually necessitates additional measurements and averaging. However, without the proper modeling and analysis, repeating the measurement and averaging results alone will not guarantee the accuracy. In this paper, we analyze root causes of the error for the PDL current measurements. Our analysis indicates that while quantization error and thermal noise have negligible impact on the error of the measurements, the instrument accuracy, timing, and temperature based variation are the major contributors to accuracy. We develop a new accuracy model for the PDL current measurement to account for these major contributors. Using this model, we propose a new systematic optimization method for the test process to achieve the desired accuracy without increasing the test time unreasonably. This method and the model are empirically verified with hardware experiments. With hardware experiments we also show that we can reduce the test time nearly 3-fold using the optimized test sequencing strategy.
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U2 - 10.1109/VTS.2014.6818786
DO - 10.1109/VTS.2014.6818786
M3 - Conference contribution
AN - SCOPUS:84901940361
SN - 9781479926114
T3 - Proceedings of the IEEE VLSI Test Symposium
BT - Proceedings - 2014 IEEE 32nd VLSI Test Symposium, VTS 2014
PB - IEEE Computer Society
T2 - 2014 IEEE 32nd VLSI Test Symposium, VTS 2014
Y2 - 13 April 2014 through 17 April 2014
ER -