Compact modeling and simulation of circuit reliability for 65-nm CMOS technology

Keyphrases

• Circuit Reliability 100%
• Compact Modeling 100%
• 65nm CMOS 100%
• Channel Hot Carrier 100%
• Negative Bias Temperature Instability 75%
• 65 Nm Technology 50%
• Circuit Performance 25%
• Performance Degradation 25%
• Surface Potential 25%
• Reaction-diffusion Model 25%
• De-facto 25%
• Process Conditions 25%
• Design Condition 25%
• Modeling Method 25%
• Ring Oscillator 25%
• Unified Approach 25%
• Technology Scaling 25%
• Subthreshold 25%
• Hot Carrier Effect 25%
• Nanoscale Transistor 25%
• Transistor Parameters 25%
• Substrate Current 25%
• Strong Inversion Region 25%
• Circuit Performance Degradation 25%

Engineering

• Negative-Bias Temperature Instability 100%
• Circuit Performance 66%
• Performance Degradation 66%
• Amplifier 33%
• Nanoscale 33%
• Process Condition 33%
• Design Condition 33%
• Surface Potential 33%
• Carrier Effect 33%
• Reaction-Diffusion Model 33%
• Strong Inversion 33%
• Oscillator 33%