Compact modeling and simulation of circuit reliability for 65-nm CMOS technology

Wenping Wang, Vijay Reddy, Anand T. Krishnan, Rakesh Vattikonda, Srikanth Krishnan, Yu Cao

Research output: Contribution to journalArticlepeer-review

290 Scopus citations


Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are the leading reliability concerns for nanoscale transistors. The de facto modeling method to analyze CHC is based on substrate current Isub, which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this paper, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions for both NBTI and CHC effects. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65-nm technology. By benchmarking the prediction of circuit performance degradation with the measured ring oscillator data and simulations of an amplifier, we demonstrate that the proposed method very well predicts the degradation. For 65-nm technology, NBTI is the dominant reliability concern, and the impact of CHC on circuit performance is relatively small.

Original languageEnglish (US)
Pages (from-to)509-517
Number of pages9
JournalIEEE Transactions on Device and Materials Reliability
Issue number4
StatePublished - Dec 2007


  • Channel hot carrier (CHC)
  • Circuit
  • Interface traps
  • Negative bias temperature instability (NBTI)
  • Performance
  • Reaction-diffusion (R-D) model
  • Simulation

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering


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