An ADC-BiST scheme using sequential code analysis

Erdem S. Erdogan, Sule Ozev

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Scopus citations


This paper presents a built-in self-test (BiST) scheme for analog to digital converters (ADC) based on a linear ramp generator and efficient output analysis. The proposed analysis method is an alternative to histogram based analysis techniques to provide test time improvements, especially when the resources are scarce. In addition to the measurement of DNL and INL non-monotonic behavior can also be detected with the proposed technique. We present two implementation options based on how much on-chip resources are available. The ramp generator has a high linearity over a full-scale range of IV and the generated ramp signal is capable of testing 13 - bit ADCs. The circuit implementation of the ramp generator utilizes a feedback configuration to improve the linearity having an area of 0.017mm2 in 0.5μm process.

Original languageEnglish (US)
Title of host publicationProceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007
Number of pages6
StatePublished - 2007
Externally publishedYes
Event2007 Design, Automation and Test in Europe Conference and Exhibition - Nice Acropolis, France
Duration: Apr 16 2007Apr 20 2007

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591


Other2007 Design, Automation and Test in Europe Conference and Exhibition
CityNice Acropolis

ASJC Scopus subject areas

  • General Engineering


Dive into the research topics of 'An ADC-BiST scheme using sequential code analysis'. Together they form a unique fingerprint.

Cite this