A robust, self-tuning CMOS circuit for built-in go/no-go testing of synthesizer phase noise

Mathematics

• Phase Noise 100%
• Self-tuning 85%
• Phase-locked Loop 44%
• Testing 40%
• Built-in Self-test 36%
• Low-frequency Noise 20%
• Self-calibration 16%
• NAND 16%
• Analog Circuits 15%
• Process Variation 14%
• Jitter 14%
• Chip 12%
• Timing 11%
• Voltage 10%
• Monte Carlo Simulation 8%
• Target 8%
• Output 7%
• Analogue 6%

Engineering & Materials Science

• Phase noise 61%
• Tuning 44%
• Networks (circuits) 31%
• Phase locked loops 29%
• Testing 29%
• Built-in self test 23%
• Timing jitter 13%
• Analog circuits 10%
• Variable frequency oscillators 10%
• Clocks 8%
• Calibration 7%