TY - JOUR
T1 - A Reconfigurable 0.1-10 MHz DT Passive Dynamic Zoom ADC for Cellular Receivers
AU - Erol, Osman Emir
AU - Ozev, Sule
N1 - Funding Information:
Manuscript received December 27, 2019; revised February 13, 2020; accepted February 16, 2020. Date of publication February 28, 2020; date of current version July 1, 2020. This work was supported in part by the National Science Foundation under Grant 1617562 and in part by Semiconductor Research Corporation under Task 2712.003. This article was recommended by Associate Editor L. Hernandez. (Corresponding author: Osman Emir Erol.) Osman Emir Erol was with the School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ 85201 USA. He is now with the Synaptics Corporation, San Jose, CA 95131 USA (e-mail: osman.erol@asu.edu).
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2020/7
Y1 - 2020/7
N2 - This paper presents a multi-mode, dynamically zooming analog to digital converter (ADC). The architecture is based on a 5b interpolating flash ADC as the zooming unit and a passive discrete-time Δ Σ modulator as the fine conversion unit. The proposed ADC provides a dynamic zooming technique, employing an interpolating zooming front-end. The modulator covers between 0.1 MHz and 10 MHz signal bandwidth which makes it suitable for cellular applications including 4G radio systems. By reconfiguring the OSR, bias current, and component parameters, optimal power consumption can be achieved for every mode. The ADC is implemented in 0.13 μ m CMOS technology and it achieves an SNDR of 83/75.7/73.2/67 dB for 0.1/1.92/5/10MHz bandwidth with 1.3/4.7/8.1/10.3mW power consumption from a 1.2 V supply.
AB - This paper presents a multi-mode, dynamically zooming analog to digital converter (ADC). The architecture is based on a 5b interpolating flash ADC as the zooming unit and a passive discrete-time Δ Σ modulator as the fine conversion unit. The proposed ADC provides a dynamic zooming technique, employing an interpolating zooming front-end. The modulator covers between 0.1 MHz and 10 MHz signal bandwidth which makes it suitable for cellular applications including 4G radio systems. By reconfiguring the OSR, bias current, and component parameters, optimal power consumption can be achieved for every mode. The ADC is implemented in 0.13 μ m CMOS technology and it achieves an SNDR of 83/75.7/73.2/67 dB for 0.1/1.92/5/10MHz bandwidth with 1.3/4.7/8.1/10.3mW power consumption from a 1.2 V supply.
KW - Analog-to-digital converter (ADC)
KW - dynamic zoom ADC
KW - passive delta-sigma (ΔΣ) modulators
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U2 - 10.1109/TCSI.2020.2975890
DO - 10.1109/TCSI.2020.2975890
M3 - Article
AN - SCOPUS:85088121414
SN - 1549-8328
VL - 67
SP - 2216
EP - 2228
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 7
M1 - 9018200
ER -