TY - GEN
T1 - Yield optimization with energy-delay constraints in low-power digital circuits
AU - Cao, Yu
AU - Qin, Huifang
AU - Wang, Ruth
AU - Friedberg, Paul
AU - Vladimirescu, Andrei
AU - Rabaey, Jan
PY - 2003/1/1
Y1 - 2003/1/1
N2 - As circuit parametric variations aggravate in advanced technology, yield emerges as an important figure-of-merit in circuit design. Based on a 130nm technology, the yield-energy-delay tradeoffs in low-power circuit optimization are investigated. Using a log-normal statistical model, Monte-Carlo analyses are performed on typical circuit examples, including an inverter chain, NAND gate, and 4-bit adder. While energy reduction can be effectively achieved by tuning supply voltage (Vdd), threshold voltage (Vtb), and device width (W), circuit yield degrades during this process. On the other hand, it is observed that performance variability is relatively insensitive to circuit topology and device length (L). Design guidelines for optimizing yield in the presence of parametric variations and energy-delay constraints are proposed.
AB - As circuit parametric variations aggravate in advanced technology, yield emerges as an important figure-of-merit in circuit design. Based on a 130nm technology, the yield-energy-delay tradeoffs in low-power circuit optimization are investigated. Using a log-normal statistical model, Monte-Carlo analyses are performed on typical circuit examples, including an inverter chain, NAND gate, and 4-bit adder. While energy reduction can be effectively achieved by tuning supply voltage (Vdd), threshold voltage (Vtb), and device width (W), circuit yield degrades during this process. On the other hand, it is observed that performance variability is relatively insensitive to circuit topology and device length (L). Design guidelines for optimizing yield in the presence of parametric variations and energy-delay constraints are proposed.
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U2 - 10.1109/EDSSC.2003.1283533
DO - 10.1109/EDSSC.2003.1283533
M3 - Conference contribution
AN - SCOPUS:14844302557
T3 - 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
SP - 285
EP - 288
BT - 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
Y2 - 16 December 2003 through 18 December 2003
ER -