Abstract
The degradation of IC reliability is usually a gradual process, only causing moderate increase in the failure rate over time. However, under some specific circumstance, the degradation rate can be dramatically accelerated, leading to some catastrophic phenomena in digital and analog designs. Based on silicon data, this paper highlights such critical conditions, including severe frequency shift under DVS, asymmetric aging due to clock gating, and bias runaway. The analysis and solutions to these issues are vitally important to reliable IC design practice.
Original language | English (US) |
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Title of host publication | Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI |
Publisher | IEEE Computer Society |
Pages | 278-279 |
Number of pages | 2 |
ISBN (Electronic) | 9781479937639 |
DOIs | |
State | Published - Sep 18 2014 |
Event | 2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014 - Tampa, United States Duration: Jul 9 2014 → Jul 11 2014 |
Other
Other | 2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014 |
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Country/Territory | United States |
City | Tampa |
Period | 7/9/14 → 7/11/14 |
Keywords
- BTI
- DVS
- HCI
- asymmetric aging
- bias runaway
- circuit aging
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering
- Electrical and Electronic Engineering