Voltage-frequency island partitioning for GALS-based networks-on-chip

Umit Y. Ogras, Radu Marculescu, Puru Choudhary, Diana Marculescu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

124 Scopus citations


Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single global clock signal throughout a chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design is considered for achieving low power consumption and modular design. Such a design style fits nicely with the concept of voltage-frequency islands (VFIs) which has been recently introduced for achieving fine-grain system-level power management. This paper proposes a design methodology for partitioning an NoC architecture into multiple VFIs and assigning supply and threshold voltage levels to each VFI. Simulation results show about 40% savings for a real video application and demonstrate the effectiveness of our approach in reducing the overall system energy consumption. The results and functional correctness are validated using an FPGA prototype for an NoC with multiple VFIs.

Original languageEnglish (US)
Title of host publication2007 44th ACM/IEEE Design Automation Conference, DAC'07
Number of pages6
StatePublished - 2007
Externally publishedYes
Event2007 44th ACM/IEEE Design Automation Conference, DAC'07 - San Diego, CA, United States
Duration: Jun 4 2007Jun 8 2007

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Other2007 44th ACM/IEEE Design Automation Conference, DAC'07
Country/TerritoryUnited States
CitySan Diego, CA


  • GALS
  • Multi-processor systems
  • Networks-on-chip
  • Voltage-frequency island

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering


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