Abstract
A new structure for the VLSI implementation of a bit/serial adaptive IIR filter is presented. The system is built at a bit level consisting of only gated full adders. This approach allows recursive operation of the IIR filter to be implemented with minimal delay time and chip area. The coefficients of the filter can be updated in real time for the time invariant and adaptive filtering. The fourth-order filter is implemented on a 2-μm CMOS technology clocked at 50 MHz.
| Original language | English (US) |
|---|---|
| Title of host publication | IEEE Pacific RIM Conf Commun Comput Signal Process |
| Editors | Anon |
| Place of Publication | Piscataway, NJ, United States |
| Publisher | Publ by IEEE |
| Pages | 650-652 |
| Number of pages | 3 |
| State | Published - 1989 |
| Externally published | Yes |
| Event | IEEE Pacific RIM Conference on Communications, Computers and Signal Processing - Victoria, BC, Canada Duration: Jun 1 1989 → Jun 2 1989 |
Other
| Other | IEEE Pacific RIM Conference on Communications, Computers and Signal Processing |
|---|---|
| City | Victoria, BC, Canada |
| Period | 6/1/89 → 6/2/89 |
ASJC Scopus subject areas
- Engineering(all)