VLSI design of dynamically reconfigurable array processor-DRAP

Sayfe Kiaei; Jaisimha K. Durgam

VLSI design of dynamically reconfigurable array processor-DRAP

Sayfe Kiaei, Jaisimha K. Durgam

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A novel 2-D bidirectional, reconfigurable systolic array is presented. The system can be easily reconfigured and applied in many DSP and matrix processing applications. The different interconnection schemes are achieved by a set of simple local switches that contributes only a 15% increase in the chip area. The processor was implemented in 2-μm CMOS technology and was tested for 1-D linear, 2-D square-mesh, and 2-D hexagonal structures. Another feature of this system is that its configuration patterns can be expanded to support additional algorithms.

Original language	English (US)
Title of host publication	ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Editors	Anon
Publisher	Publ by IEEE
Pages	2484-2488
Number of pages	5
Volume	4
State	Published - 1989
Externally published	Yes
Event	1989 International Conference on Acoustics, Speech, and Signal Processing - Glasgow, Scotland Duration: May 23 1989 → May 26 1989

Other

Other	1989 International Conference on Acoustics, Speech, and Signal Processing
City	Glasgow, Scotland
Period	5/23/89 → 5/26/89

ASJC Scopus subject areas

Signal Processing
Electrical and Electronic Engineering
Acoustics and Ultrasonics

Cite this

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title = "VLSI design of dynamically reconfigurable array processor-DRAP",

abstract = "A novel 2-D bidirectional, reconfigurable systolic array is presented. The system can be easily reconfigured and applied in many DSP and matrix processing applications. The different interconnection schemes are achieved by a set of simple local switches that contributes only a 15% increase in the chip area. The processor was implemented in 2-μm CMOS technology and was tested for 1-D linear, 2-D square-mesh, and 2-D hexagonal structures. Another feature of this system is that its configuration patterns can be expanded to support additional algorithms.",

author = "Sayfe Kiaei and Durgam, {Jaisimha K.}",

year = "1989",

language = "English (US)",

volume = "4",

pages = "2484--2488",

editor = "Anon",

booktitle = "ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings",

publisher = "Publ by IEEE",

note = "1989 International Conference on Acoustics, Speech, and Signal Processing ; Conference date: 23-05-1989 Through 26-05-1989",

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AU - Kiaei, Sayfe

AU - Durgam, Jaisimha K.

PY - 1989

Y1 - 1989

N2 - A novel 2-D bidirectional, reconfigurable systolic array is presented. The system can be easily reconfigured and applied in many DSP and matrix processing applications. The different interconnection schemes are achieved by a set of simple local switches that contributes only a 15% increase in the chip area. The processor was implemented in 2-μm CMOS technology and was tested for 1-D linear, 2-D square-mesh, and 2-D hexagonal structures. Another feature of this system is that its configuration patterns can be expanded to support additional algorithms.

AB - A novel 2-D bidirectional, reconfigurable systolic array is presented. The system can be easily reconfigured and applied in many DSP and matrix processing applications. The different interconnection schemes are achieved by a set of simple local switches that contributes only a 15% increase in the chip area. The processor was implemented in 2-μm CMOS technology and was tested for 1-D linear, 2-D square-mesh, and 2-D hexagonal structures. Another feature of this system is that its configuration patterns can be expanded to support additional algorithms.

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UR - http://www.scopus.com/inward/citedby.url?scp=0024876973&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0024876973

VL - 4

SP - 2484

EP - 2488

BT - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

A2 - Anon, null

PB - Publ by IEEE

T2 - 1989 International Conference on Acoustics, Speech, and Signal Processing

Y2 - 23 May 1989 through 26 May 1989

ER -

VLSI design of dynamically reconfigurable array processor-DRAP

Abstract

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ASJC Scopus subject areas

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