VLSI architecture for discrete wavelet transform

A. Grzeszczak, T. H. Yeap, S. Panchanathan

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations


This paper presents a new VLSI architecture for computing the Discrete Wavelet Transform (DWT). The architecture is systolic in nature and utilizes a frequency doubler, which enables it to perform all coefficient calculations with only one set of multipliers, in contrast to the approaches presented in the literature [1], [2], [3]. The architecture is simple, modular, and cascadable, and hence can be implemented in VLSI.

Original languageEnglish (US)
Pages (from-to)461-464
Number of pages4
JournalCanadian Conference on Electrical and Computer Engineering
StatePublished - 1994
Externally publishedYes
EventProceedings of the 1994 Canadian Conference on Electrical and Computer Engineering. Part 2 (of 2) - Halifax, Can
Duration: Sep 25 1994Sep 28 1994

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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