Abstract
This paper presents a new VLSI architecture for computing the Discrete Wavelet Transform (DWT). The architecture is systolic in nature and utilizes a frequency doubler, which enables it to perform all coefficient calculations with only one set of multipliers, in contrast to the approaches presented in the literature [1], [2], [3]. The architecture is simple, modular, and cascadable, and hence can be implemented in VLSI.
Original language | English (US) |
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Pages (from-to) | 461-464 |
Number of pages | 4 |
Journal | Canadian Conference on Electrical and Computer Engineering |
Volume | 2 |
DOIs | |
State | Published - 1994 |
Externally published | Yes |
Event | Proceedings of the 1994 Canadian Conference on Electrical and Computer Engineering. Part 2 (of 2) - Halifax, Can Duration: Sep 25 1994 → Sep 28 1994 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering