VLSI architecture for DFT

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations


In this paper, a one-dimensional fully pipelined architecture for computing discrete-Fourier transform (DFT) is presented. It consists of an array of N basic cells (BC's) and requires N clock cycles for a N-point DFT. The architecture is modular and makes possible computation of a 2N-point transform by a simple cascade of two identical N-point transform chips. The architecture is simple and regular in structure and is hence very attractive for VLSI implementation.

Original languageEnglish (US)
Title of host publicationMidwest Symposium on Circuits and Systems
PublisherPubl by IEEE
Number of pages4
ISBN (Print)0780317610
StatePublished - Dec 1 1993
Externally publishedYes
EventProceedings of the 36th Midwest Symposium on Circuits and Systems - Detroit, MI, USA
Duration: Aug 16 1993Aug 18 1993

Publication series

NameMidwest Symposium on Circuits and Systems


OtherProceedings of the 36th Midwest Symposium on Circuits and Systems
CityDetroit, MI, USA

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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