@inproceedings{73f315f3b82f4979bef4acfeba7545b0,
title = "Vertical p-channel double-gate MOSFETs",
abstract = "Double-gate MOSFETs have drawn increasing interest within the last years because of their capability to reduce short channel effects. In this work a p-channel double-gate MOSFET layout was realised. Based on epitaxial growth and subsequent ion implantation, the p/n/p-doping profile is implemented in vertical sequence. P-channel devices with channel lengths of 50 nm and gate oxide thickness of 6.6 nm show transconductances of 480 μS/μm, subthreshold slope of 126 mV/dec and DIBL of 80 mV/V.",
author = "J. Moers and S. Trellenkamp and Avd Hart and M. Goryll and S. Mantl and P. Kordos and H. Luth",
note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; 33rd European Solid-State Device Research Conference, ESSDERC 2003 ; Conference date: 16-09-2003 Through 18-09-2003",
year = "2003",
doi = "10.1109/ESSDERC.2003.1256831",
language = "English (US)",
isbn = "9780780379992",
series = "European Solid-State Device Research Conference",
publisher = "IEEE Computer Society",
pages = "143--146",
editor = "Jose Franca and Paulo Freitas",
booktitle = "ESSDERC 2003 - Proceedings of the 33rd European Solid-State Device Research Conference",
}