Variability induced by line edge roughness in double-gate dopant-segregated schottky MOSFETs

Yunxiang Yang, Shimeng Yu, Lang Zeng, Gang Du, Jinfeng Kang, Yuning Zhao, Ruqi Han, Xiaoyan Liu

Research output: Contribution to journalArticlepeer-review

5 Scopus citations


Intrinsic parameter fluctuations introduced by process variations, such as line edge roughness (LER), create an increasing challenge to the CMOS technology scaling. In this paper, variations in double-gate dopant-segregate Schottky (DSS) MOSFETs, caused by LER of silicon-fin, are systematically investigated using statistical technology computer-aided design simulations. The impact of LER on both Schottky barrier and DSS-MOSFETs are examined contrastively. The results show that DSS-MOSFETs offer a larger and more uniform drive current, but suffer a more serious Vt fluctuation. The cause of such larger Vt flutuation is also analyzed, thus providing a good starting point to propose way to solve this problem.

Original languageEnglish (US)
Article number5353696
Pages (from-to)244-249
Number of pages6
JournalIEEE Transactions on Nanotechnology
Issue number2
StatePublished - Mar 2011
Externally publishedYes


  • Dopant-segregated Schottky MOSFETs (DSS-MOSFETs)
  • Schottky barrier (SB)
  • line edge roughness (LER)
  • technology computer-aided design (TCAD) simulation
  • variations

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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