Transpose-free SAR imaging on FPGA platform

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations


Range-Doppler Algorithm (RDA) and Chirp Scaling Algorithm (CSA) are two widely used Synthetic Aperture Radar (SAR) imaging schemes. Both require multiple transpose operations which increase the total processing time significantly. In this paper, we propose transpose-free flow for both RDA and CSA. This is achieved by modifying the existing flows in order to utilize the access patterns favored by the external memory. As a result, the peak performance of the memory is sustained and the processing time shortened. The proposed Field Programmable Gate Array (FPGA)-based implementation outperforms the existing SAR accelerators; it computes RDA and CSA on data size of 4, 096 × 4, 096 in 323ms and 162ms, respectively.

Original languageEnglish (US)
Title of host publicationISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems
Number of pages4
StatePublished - 2012
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: May 20 2012May 23 2012


Other2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/TerritoryKorea, Republic of


  • DRAM
  • FFT
  • FPGA
  • SAR

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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