The role of the temperature boundary conditions on the gate electrode on the heat distribution in 25 nm FD-SOI MOSFETs with SiO2 and gate-stack (high-k dielectric) as the gate oxide

Katerina Raleva; Dragica Vasileska; Stephen Goodnick

doi:10.1109/ISDRS.2007.4422323

The role of the temperature boundary conditions on the gate electrode on the heat distribution in 25 nm FD-SOI MOSFETs with SiO₂ and gate-stack (high-k dielectric) as the gate oxide

Katerina Raleva, Dragica Vasileska, Stephen Goodnick

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Original language	English (US)
Title of host publication	2007 International Semiconductor Device Research Symposium, ISDRS
DOIs	https://doi.org/10.1109/ISDRS.2007.4422323
State	Published - Dec 1 2007
Event	2007 International Semiconductor Device Research Symposium, ISDRS - College Park, MD, United States Duration: Dec 12 2007 → Dec 14 2007

Publication series

Name	2007 International Semiconductor Device Research Symposium, ISDRS

Other

Other	2007 International Semiconductor Device Research Symposium, ISDRS
Country/Territory	United States
City	College Park, MD
Period	12/12/07 → 12/14/07

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ISDRS.2007.4422323

Cite this

Raleva, K., Vasileska, D., & Goodnick, S. (2007). The role of the temperature boundary conditions on the gate electrode on the heat distribution in 25 nm FD-SOI MOSFETs with SiO₂ and gate-stack (high-k dielectric) as the gate oxide. In 2007 International Semiconductor Device Research Symposium, ISDRS Article 4422323 (2007 International Semiconductor Device Research Symposium, ISDRS). https://doi.org/10.1109/ISDRS.2007.4422323

The role of the temperature boundary conditions on the gate electrode on the heat distribution in 25 nm FD-SOI MOSFETs with SiO₂ and gate-stack (high-k dielectric) as the gate oxide. / Raleva, Katerina; Vasileska, Dragica ; Goodnick, Stephen.
2007 International Semiconductor Device Research Symposium, ISDRS. 2007. 4422323 (2007 International Semiconductor Device Research Symposium, ISDRS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Raleva, K, Vasileska, D & Goodnick, S 2007, The role of the temperature boundary conditions on the gate electrode on the heat distribution in 25 nm FD-SOI MOSFETs with SiO₂ and gate-stack (high-k dielectric) as the gate oxide. in 2007 International Semiconductor Device Research Symposium, ISDRS., 4422323, 2007 International Semiconductor Device Research Symposium, ISDRS, 2007 International Semiconductor Device Research Symposium, ISDRS, College Park, MD, United States, 12/12/07. https://doi.org/10.1109/ISDRS.2007.4422323

Raleva K, Vasileska D , Goodnick S. The role of the temperature boundary conditions on the gate electrode on the heat distribution in 25 nm FD-SOI MOSFETs with SiO₂ and gate-stack (high-k dielectric) as the gate oxide. In 2007 International Semiconductor Device Research Symposium, ISDRS. 2007. 4422323. (2007 International Semiconductor Device Research Symposium, ISDRS). doi: 10.1109/ISDRS.2007.4422323

Raleva, Katerina ; Vasileska, Dragica ; Goodnick, Stephen. / The role of the temperature boundary conditions on the gate electrode on the heat distribution in 25 nm FD-SOI MOSFETs with SiO₂ and gate-stack (high-k dielectric) as the gate oxide. 2007 International Semiconductor Device Research Symposium, ISDRS. 2007. (2007 International Semiconductor Device Research Symposium, ISDRS).

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