TY - GEN
T1 - The damage mitigation process for Si nanopillar structure using silica nanosphere lithography and metal assisted chemical etching
AU - Kim, Sangpyeong
AU - Dahal, Som
AU - Augusto, Andre
AU - Bowden, Stuart
AU - Honsberg, Christiana
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/11/26
Y1 - 2018/11/26
N2 - This work focuses on mitigating the damage from nanostructure fabrication using silica nanosphere lithography (SNL) and metal assisted chemical etching (MACE). Metal contamination and plasma damage are the two main factors to limit the Si wafer's minority carrier lifetime. Ni/Au and Ti/Au metal layers on bare Si wafer are compared using lifetime recovery test. Ti/Au shows to be more suitable for the MACE process. Samples deposited with Ni/Au and Ti/Au show lifetimes of 7 \mu \mathrm{s} and 1200 \mu \mathrm{s}, respectively. The silicon surfaceis degraded significantly by the RIE plasma during the nanosphere etching process. SiO2 protective layer was added to the process, mitigating significantly the plasma damage on the siliconsurface. Lifetime measurements shows an improvement over 1 ms when SiO2 protective layer on planar Si wafer is used. Lifetimes of 353 \mu \mathrm{s} and implied open circuit voltages of 651mV were accomplished on nanopillar structured wafers using SiOx protective layer and Ti/Au.
AB - This work focuses on mitigating the damage from nanostructure fabrication using silica nanosphere lithography (SNL) and metal assisted chemical etching (MACE). Metal contamination and plasma damage are the two main factors to limit the Si wafer's minority carrier lifetime. Ni/Au and Ti/Au metal layers on bare Si wafer are compared using lifetime recovery test. Ti/Au shows to be more suitable for the MACE process. Samples deposited with Ni/Au and Ti/Au show lifetimes of 7 \mu \mathrm{s} and 1200 \mu \mathrm{s}, respectively. The silicon surfaceis degraded significantly by the RIE plasma during the nanosphere etching process. SiO2 protective layer was added to the process, mitigating significantly the plasma damage on the siliconsurface. Lifetime measurements shows an improvement over 1 ms when SiO2 protective layer on planar Si wafer is used. Lifetimes of 353 \mu \mathrm{s} and implied open circuit voltages of 651mV were accomplished on nanopillar structured wafers using SiOx protective layer and Ti/Au.
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U2 - 10.1109/PVSC.2018.8548297
DO - 10.1109/PVSC.2018.8548297
M3 - Conference contribution
AN - SCOPUS:85059894307
T3 - 2018 IEEE 7th World Conference on Photovoltaic Energy Conversion, WCPEC 2018 - A Joint Conference of 45th IEEE PVSC, 28th PVSEC and 34th EU PVSEC
SP - 3121
EP - 3124
BT - 2018 IEEE 7th World Conference on Photovoltaic Energy Conversion, WCPEC 2018 - A Joint Conference of 45th IEEE PVSC, 28th PVSEC and 34th EU PVSEC
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th IEEE World Conference on Photovoltaic Energy Conversion, WCPEC 2018
Y2 - 10 June 2018 through 15 June 2018
ER -