Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip

Keyphrases

• Technology Design 100%
• Learning Algorithm 100%
• On chip 100%
• Co-optimization 100%
• Cross-point Array 100%
• Learning Accuracy 60%
• Latency 40%
• Energy Consumption 20%
• Machine Learning Algorithms 20%
• Peripheral Circuits 20%
• Sparse Coding 20%
• Energy Efficiency Improvement 20%
• Design Parameters 20%
• Multi-cell 20%
• Memory Design 20%
• Weight Update 20%
• IR Drop 20%
• Gradient-based 20%
• Training Process 20%
• Higher Learning 20%
• Weighted Sums 20%
• Optimization Methodology 20%
• Scaling Rule 20%
• Time-image 20%
• Parallel Operation 20%
• Technology Parameters 20%
• Fully Parallel 20%
• Image Feature Extraction 20%
• Wire Width 20%
• Read Scheme 20%
• Device Variations 20%
• Handwritten Digit Recognition 20%
• Image Feature Learning 20%
• MNIST Dataset 20%
• Write Scheme 20%

Computer Science

• Learning Algorithm 100%
• Technology Design 100%
• Energy Consumption 50%
• Energy Efficiency 50%
• Machine Learning Algorithm 50%
• Speed-up 50%
• Design Parameter 50%
• Memory Design 50%
• image feature 50%
• Training Process 50%
• Parallel Operation 50%
• handwritten digit recognition 50%
• Feature Extraction 50%