Technological Benchmark of Analog Synaptic Devices for Neuroinspired Architectures

Pai Yu Chen; Shimeng Yu

doi:10.1109/MDAT.2018.2890229

Technological Benchmark of Analog Synaptic Devices for Neuroinspired Architectures

Pai Yu Chen, Shimeng Yu

Arizona State University

Research output: Contribution to journal › Article › peer-review

31 Scopus citations

Abstract

Editor's note: In this article, the authors present a circuit-level macro model ('NeuroSim' simulator) to estimate circuit-level performance of neuroinspired architectures to facilitate design space exploration. The model is used to analyze the impact of analog synapse device characteristics on the performance of a two-layer multi-layer perceptron (MLP) neural network and identify critical device properties (on/off ratio and asymmetry, in this case) to guide technology development. - An Chen, Semiconductor Research Corporation.

Original language	English (US)
Article number	8594608
Pages (from-to)	31-38
Number of pages	8
Journal	IEEE Design and Test
Volume	36
Issue number	3
DOIs	https://doi.org/10.1109/MDAT.2018.2890229
State	Published - Jun 2019

Keywords

Neuromorphic computing
ferroelectric transistor
machine learning
neural network
non-volatile memory
phase change memory
resistive memory
synaptic devices

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/MDAT.2018.2890229

Cite this

@article{b5544a54cc3c4dbf8c924de7742b3865,

title = "Technological Benchmark of Analog Synaptic Devices for Neuroinspired Architectures",

abstract = "Editor's note: In this article, the authors present a circuit-level macro model ('NeuroSim' simulator) to estimate circuit-level performance of neuroinspired architectures to facilitate design space exploration. The model is used to analyze the impact of analog synapse device characteristics on the performance of a two-layer multi-layer perceptron (MLP) neural network and identify critical device properties (on/off ratio and asymmetry, in this case) to guide technology development. - An Chen, Semiconductor Research Corporation.",

keywords = "Neuromorphic computing, ferroelectric transistor, machine learning, neural network, non-volatile memory, phase change memory, resistive memory, synaptic devices",

author = "Chen, {Pai Yu} and Shimeng Yu",

note = "Funding Information: This work was supported in part by NSF-CCF-1552687, NSF-CCF-1740225, NSF/SRC E2CDA program, and in part by ASCENT, one of the six SRC/DARPA JUMP Centers. We would like to thank Prof. S. Datta from the University of Notre Dame for discussions on the ferroelectric field-effect transistor. Publisher Copyright: {\textcopyright} 2019 IEEE.",

year = "2019",

month = jun,

doi = "10.1109/MDAT.2018.2890229",

language = "English (US)",

volume = "36",

pages = "31--38",

journal = "IEEE Design and Test",

issn = "2168-2356",

publisher = "IEEE Computer Society",

number = "3",

}

TY - JOUR

T1 - Technological Benchmark of Analog Synaptic Devices for Neuroinspired Architectures

AU - Chen, Pai Yu

AU - Yu, Shimeng

N1 - Funding Information: This work was supported in part by NSF-CCF-1552687, NSF-CCF-1740225, NSF/SRC E2CDA program, and in part by ASCENT, one of the six SRC/DARPA JUMP Centers. We would like to thank Prof. S. Datta from the University of Notre Dame for discussions on the ferroelectric field-effect transistor. Publisher Copyright: © 2019 IEEE.

PY - 2019/6

Y1 - 2019/6

N2 - Editor's note: In this article, the authors present a circuit-level macro model ('NeuroSim' simulator) to estimate circuit-level performance of neuroinspired architectures to facilitate design space exploration. The model is used to analyze the impact of analog synapse device characteristics on the performance of a two-layer multi-layer perceptron (MLP) neural network and identify critical device properties (on/off ratio and asymmetry, in this case) to guide technology development. - An Chen, Semiconductor Research Corporation.

AB - Editor's note: In this article, the authors present a circuit-level macro model ('NeuroSim' simulator) to estimate circuit-level performance of neuroinspired architectures to facilitate design space exploration. The model is used to analyze the impact of analog synapse device characteristics on the performance of a two-layer multi-layer perceptron (MLP) neural network and identify critical device properties (on/off ratio and asymmetry, in this case) to guide technology development. - An Chen, Semiconductor Research Corporation.

KW - Neuromorphic computing

KW - ferroelectric transistor

KW - machine learning

KW - neural network

KW - non-volatile memory

KW - phase change memory

KW - resistive memory

KW - synaptic devices

UR - http://www.scopus.com/inward/record.url?scp=85059376657&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85059376657&partnerID=8YFLogxK

U2 - 10.1109/MDAT.2018.2890229

DO - 10.1109/MDAT.2018.2890229

M3 - Article

AN - SCOPUS:85059376657

SN - 2168-2356

VL - 36

SP - 31

EP - 38

JO - IEEE Design and Test

JF - IEEE Design and Test

IS - 3

M1 - 8594608

ER -

Technological Benchmark of Analog Synaptic Devices for Neuroinspired Architectures

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this