Technological Benchmark of Analog Synaptic Devices for Neuroinspired Architectures

Pai Yu Chen, Shimeng Yu

Research output: Contribution to journalArticlepeer-review

30 Scopus citations


Editor's note: In this article, the authors present a circuit-level macro model ('NeuroSim' simulator) to estimate circuit-level performance of neuroinspired architectures to facilitate design space exploration. The model is used to analyze the impact of analog synapse device characteristics on the performance of a two-layer multi-layer perceptron (MLP) neural network and identify critical device properties (on/off ratio and asymmetry, in this case) to guide technology development. - An Chen, Semiconductor Research Corporation.

Original languageEnglish (US)
Article number8594608
Pages (from-to)31-38
Number of pages8
JournalIEEE Design and Test
Issue number3
StatePublished - Jun 2019


  • Neuromorphic computing
  • ferroelectric transistor
  • machine learning
  • neural network
  • non-volatile memory
  • phase change memory
  • resistive memory
  • synaptic devices

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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