Target architecture automation for reconfigurable logic blocks

This paper proposes the design of a tool that automates the generation of the target architecture onto which reconfigurable logic blocks are mapped. The target architecture is hierarchical in nature and includes both the number and complexity of the interconnect switches at each level. The architecture is generated based on our proposed vector space model for representing interconnections between reconfigurable blocks. The automation is based on our modified version of constrained agglomerative hierarchical clustering that has been proven as the best hierarchical clustering approach in the field of data mining. The proposed architecture optimizes both transient and static power while meeting timing constraints.