Systolic array architecture for real-time Gabor decomposition

Giridharan Iyengar, Sethuraman Panchanathan

Research output: Chapter in Book/Report/Conference proceedingConference contribution


In this paper, we propose a combined systolic array - content addressable memory architecture for image compression using Gabor decomposition. Gabor decomposition is attractive for image compression since the basis functions match the human visual profiles. Gabor functions also achieve the lowest bound on the joint entropy of data. However these functions are not orthogonal and hence an analytic solution for the decomposition does not exist. Recently it has been shown that Gabor decomposition can be computed as a multiplication between a transform matrix and a vector of image data. Systolic arrays are attractive for matrix multiplication problems and content addressable memories (CAM) offer fast means of data access. For an n × n image, the proposed architecture for Gabor decomposition consists of a linear systolic array of n processing elements each with a local CAM. Simulations and complexity studies show that this architecture can achieve real-time performance with current technology. This architecture is modular and regular and hence it can be implemented in VLSI as a codec.

Original languageEnglish (US)
Title of host publicationProceedings of SPIE - The International Society for Optical Engineering
PublisherPubl by Int Soc for Optical Engineering
Number of pages10
Editionpt 3
ISBN (Print)0819410187
StatePublished - 1992
Externally publishedYes
EventVisual Communications and Image Processing '92 - Boston, MA, USA
Duration: Nov 18 1992Nov 20 1992

Publication series

NameProceedings of SPIE - The International Society for Optical Engineering
Numberpt 3
ISSN (Print)0277-786X


OtherVisual Communications and Image Processing '92
CityBoston, MA, USA

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Computer Science Applications
  • Applied Mathematics
  • Electrical and Electronic Engineering


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