Abstract
This paper proposes two-dimensional systolic array implementations for computing the discrete Hartley (DHT) and the discrete cosine transforms (DCT) when the transform size A’ is decomposable into mutually prime factors. The existing two-dimensional formulations for DHT and DCT are modified and the corresponding algorithms are mapped into two-dimensional systolic arrays. The resulting architecture is fully pipelined with no control units. The hardware design is based on bit serial left to right MSB to LSB binary arithmetic.
Original language | English (US) |
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Pages (from-to) | 1359-1368 |
Number of pages | 10 |
Journal | IEEE Transactions on Computers |
Volume | 39 |
Issue number | 11 |
DOIs | |
State | Published - Nov 1990 |
Externally published | Yes |
Keywords
- Architecture
- VLSI
- bit-serial
- discrete Hartley transform (DHT)
- discrete cosine transform
- prime-factor decomposition
- systolic
ASJC Scopus subject areas
- Software
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics