TY - GEN
T1 - System-level design techniques for throughput and power optimization of multiprocessor SoC architectures
AU - Srinivasan, Krishnan
AU - Telkar, Nagender
AU - Ramamurthi, Vijay
AU - Chatha, Karam S.
PY - 2004/9/24
Y1 - 2004/9/24
N2 - Innovative system-level computer-aided design techniques are required for optimizing the performance and power of applications that are mapped to multiprocessor system-on-chip (SoC) architectures. The paper addresses the hitherto unexplored problem of system-level low power design of multimedia and network processing applications with deadline greater than period. This paper presents four techniques that combine low power optimizations (namely dynamic voltage and frequency scaling (DVS) and dynamic power management (DPM)) with loop transformations (functional pipelining and unrolling) to minimize the power consumption, while satisfying the period and deadline constraints of the application. The strengths of the techniques lie in their low complexity and large power consumption savings when compared with existing heuristic based approaches, and close to optimum results when compared with our ILP based approach (presented elsewhere [1]). All our techniques result in large system-level power reductions when compared with existing heuristic approaches (max: 55.45%, min: 28.60 %, avg: 42.02 %). Further, the results produced by our deterministic and stochastic techniques for realistic benchmarks are on an average within 12.07 % and 4.125 %, respectively of the optimum solution produced by the ILP based approach. Our heuristic techniques are faster than the ILP based approach by several orders of magnitude.
AB - Innovative system-level computer-aided design techniques are required for optimizing the performance and power of applications that are mapped to multiprocessor system-on-chip (SoC) architectures. The paper addresses the hitherto unexplored problem of system-level low power design of multimedia and network processing applications with deadline greater than period. This paper presents four techniques that combine low power optimizations (namely dynamic voltage and frequency scaling (DVS) and dynamic power management (DPM)) with loop transformations (functional pipelining and unrolling) to minimize the power consumption, while satisfying the period and deadline constraints of the application. The strengths of the techniques lie in their low complexity and large power consumption savings when compared with existing heuristic based approaches, and close to optimum results when compared with our ILP based approach (presented elsewhere [1]). All our techniques result in large system-level power reductions when compared with existing heuristic approaches (max: 55.45%, min: 28.60 %, avg: 42.02 %). Further, the results produced by our deterministic and stochastic techniques for realistic benchmarks are on an average within 12.07 % and 4.125 %, respectively of the optimum solution produced by the ILP based approach. Our heuristic techniques are faster than the ILP based approach by several orders of magnitude.
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U2 - 10.1109/ISVLSI.2004.1339506
DO - 10.1109/ISVLSI.2004.1339506
M3 - Conference contribution
AN - SCOPUS:4544375965
SN - 0769520979
SN - 9780769520971
T3 - Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design
SP - 39
EP - 45
BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI
A2 - Smailagic, A.
A2 - Bayoumi, M.
T2 - Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design
Y2 - 19 February 2004 through 20 February 2004
ER -