System-level buffer allocation for application-specific networks-on-chip router design

Jingcao Hu, Umit Y. Ogras, Radu Marculescu

Research output: Contribution to journalArticlepeer-review

183 Scopus citations


In this paper, a novel system-level buffer planning algorithm that can be used to customize the router design in networks-on-chip (NoCs) is presented. More precisely, given the traffic characteristics of the target application and the total budget of the available buffering space, the proposed algorithm automatically assigns the buffer depth for each input channel, in different routers across the chip, such that the overall performance is maximized. This is in deep contrast with the uniform assignment of buffering resources (currently used in NoC design), which can significantly degrade the overall system performance. Indeed, the experimental results show that while the proposed algorithm is very fast, significant performance improvements can be achieved compared to the uniform buffer allocation. For instance, for a complex audio/video application, about 80% savings in buffering resources, can be achieved by smart buffer allocation using the proposed algorithm.

Original languageEnglish (US)
Pages (from-to)2919-2933
Number of pages15
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number12
StatePublished - Dec 2006
Externally publishedYes


  • Buffer sizing
  • Design automation
  • Low power
  • Networks-on-chip (NoCs)
  • Optimization

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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