Synthetic neural chip

R. O. Grondin, L. A. Akers, M. Walker, J. C. Wang, S. C. Chang, D. K. Ferry

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations


A compact synthetic neural cell that is compatible with CMOS technology is described. Some issues related to its applications are discussed. Particular emphasis is placed on training algorithms and connectivity. The chip architecture is presented along with the layout of a neural cell.

Original languageEnglish (US)
Title of host publicationConference Record - Asilomar Conference on Circuits, Systems & Computers
EditorsRay R. Chen
PublisherPubl by Maple Press, Inc
Number of pages5
StatePublished - 1988
Eventv 1 (of 2) - Pacific Grove, CA, USA
Duration: Oct 31 1988Nov 2 1988


Otherv 1 (of 2)
CityPacific Grove, CA, USA

ASJC Scopus subject areas

  • General Engineering

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