TY - JOUR
T1 - Structured Pruning of RRAM Crossbars for Efficient In-Memory Computing Acceleration of Deep Neural Networks
AU - Meng, Jian
AU - Yang, Li
AU - Peng, Xiaochen
AU - Yu, Shimeng
AU - Fan, Deliang
AU - Seo, Jae Sun
N1 - Funding Information:
Manuscript received February 5, 2021; accepted March 8, 2021. Date of publication March 26, 2021; date of current version April 30, 2021. This work was supported in part by National Science Foundation under Grant 1652866 and Grant 1715443; in part by Semiconductor Research Corporation AIHW Program; and in part by the C-BRIC/ASCENT, two of six centers in JUMP, a Semiconductor Research Corporation Program sponsored by DARPA. This brief was recommended by Associate Editor J. K. Eshraghian. (Corresponding author: Jae-Sun Seo.) Jian Meng, Li Yang, Deliang Fan, and Jae-Sun Seo are with the School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ 85287 USA (e-mail: jaesun.seo@asu.edu).
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2021/5
Y1 - 2021/5
N2 - The high computational complexity and a large number of parameters of deep neural networks (DNNs) become the most intensive burden of deep learning hardware design, limiting efficient storage and deployment. With the advantage of high-density storage, non-volatility, and low energy consumption, resistive RAM (RRAM) crossbar based in-memory computing (IMC) has emerged as a promising technique for DNN acceleration. To fully exploit crossbar-based IMC efficiency, a systematic compression design that considers both hardware and algorithm is necessary. In this brief, we present a system-level design considering the low precision weight and activation, structured pruning, and RRAM crossbar mapping. The proposed multi-group Lasso algorithm and hardware implementations have been evaluated on ResNet/VGG models for CIFAR-10/ImageNet datasets. With the fully quantized 4-bit ResNet-18 for CIFAR-10, we achieve up to 65.4times compression compared to full-precision software baseline, and 7times energy reduction compared to the 4-bit unpruned RRAM IMC hardware with 1.1% accuracy loss. For the fully quantized 4-bit ResNet-18 model for ImageNet dataset, we achieve up to 10.9times structured compression with 1.9% accuracy degradation.
AB - The high computational complexity and a large number of parameters of deep neural networks (DNNs) become the most intensive burden of deep learning hardware design, limiting efficient storage and deployment. With the advantage of high-density storage, non-volatility, and low energy consumption, resistive RAM (RRAM) crossbar based in-memory computing (IMC) has emerged as a promising technique for DNN acceleration. To fully exploit crossbar-based IMC efficiency, a systematic compression design that considers both hardware and algorithm is necessary. In this brief, we present a system-level design considering the low precision weight and activation, structured pruning, and RRAM crossbar mapping. The proposed multi-group Lasso algorithm and hardware implementations have been evaluated on ResNet/VGG models for CIFAR-10/ImageNet datasets. With the fully quantized 4-bit ResNet-18 for CIFAR-10, we achieve up to 65.4times compression compared to full-precision software baseline, and 7times energy reduction compared to the 4-bit unpruned RRAM IMC hardware with 1.1% accuracy loss. For the fully quantized 4-bit ResNet-18 model for ImageNet dataset, we achieve up to 10.9times structured compression with 1.9% accuracy degradation.
KW - Convolutional neural networks
KW - hardware accelerator
KW - in-memory computing
KW - resistive RAM
KW - structured pruning
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U2 - 10.1109/TCSII.2021.3069011
DO - 10.1109/TCSII.2021.3069011
M3 - Article
AN - SCOPUS:85103271159
SN - 1549-7747
VL - 68
SP - 1576
EP - 1580
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 5
M1 - 9387391
ER -