SRAM In-Memory Computing Macro With Delta-Sigma Modulator-Based Variable-Resolution Activation

Vasundhara Damodaran; Ziyu Liu; Jian Meng; Jae Sun Seo; Arindam Sanyal

doi:10.1109/LSSC.2023.3327213

SRAM In-Memory Computing Macro With Delta-Sigma Modulator-Based Variable-Resolution Activation

Vasundhara Damodaran, Ziyu Liu, Jian Meng, Jae Sun Seo, Arindam Sanyal

Research output: Contribution to journal › Article › peer-review

Abstract

This letter presents an SRAM-based compute-in-memory (CIM) macro that uses 1-bit Δ Σ modulators to convert input and output activations to binary pulse waveform. The SRAM macro uses switched-capacitors for vector matrix multiplications and together with binary input activation improves linearity compared to current-domain SRAM CIM macros and allows reconfigurable activation resolution. The proposed macro is fabricated in 65 nm and benchmarked on MNIST and CIFAR-10 datasets with accuracies of 98.67% and 89.85%, respectively, with energy-efficiency in the range of 15.4-138.6 TOPS/W.

Original language	English (US)
Pages (from-to)	293-296
Number of pages	4
Journal	IEEE Solid-State Circuits Letters
Volume	6
DOIs	https://doi.org/10.1109/LSSC.2023.3327213
State	Published - 2023
Externally published	Yes

Keywords

Compute-in-memory (CIM)
convolutional neural network (CNN)
delta-sigma
static random access memory

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/LSSC.2023.3327213

Cite this

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title = "SRAM In-Memory Computing Macro With Delta-Sigma Modulator-Based Variable-Resolution Activation",

abstract = "This letter presents an SRAM-based compute-in-memory (CIM) macro that uses 1-bit Δ Σ modulators to convert input and output activations to binary pulse waveform. The SRAM macro uses switched-capacitors for vector matrix multiplications and together with binary input activation improves linearity compared to current-domain SRAM CIM macros and allows reconfigurable activation resolution. The proposed macro is fabricated in 65 nm and benchmarked on MNIST and CIFAR-10 datasets with accuracies of 98.67% and 89.85%, respectively, with energy-efficiency in the range of 15.4-138.6 TOPS/W.",

keywords = "Compute-in-memory (CIM), convolutional neural network (CNN), delta-sigma, static random access memory",

author = "Vasundhara Damodaran and Ziyu Liu and Jian Meng and Seo, {Jae Sun} and Arindam Sanyal",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.",

year = "2023",

doi = "10.1109/LSSC.2023.3327213",

language = "English (US)",

volume = "6",

pages = "293--296",

journal = "IEEE Solid-State Circuits Letters",

issn = "2573-9603",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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TY - JOUR

T1 - SRAM In-Memory Computing Macro With Delta-Sigma Modulator-Based Variable-Resolution Activation

AU - Damodaran, Vasundhara

AU - Liu, Ziyu

AU - Meng, Jian

AU - Seo, Jae Sun

AU - Sanyal, Arindam

PY - 2023

Y1 - 2023

N2 - This letter presents an SRAM-based compute-in-memory (CIM) macro that uses 1-bit Δ Σ modulators to convert input and output activations to binary pulse waveform. The SRAM macro uses switched-capacitors for vector matrix multiplications and together with binary input activation improves linearity compared to current-domain SRAM CIM macros and allows reconfigurable activation resolution. The proposed macro is fabricated in 65 nm and benchmarked on MNIST and CIFAR-10 datasets with accuracies of 98.67% and 89.85%, respectively, with energy-efficiency in the range of 15.4-138.6 TOPS/W.

AB - This letter presents an SRAM-based compute-in-memory (CIM) macro that uses 1-bit Δ Σ modulators to convert input and output activations to binary pulse waveform. The SRAM macro uses switched-capacitors for vector matrix multiplications and together with binary input activation improves linearity compared to current-domain SRAM CIM macros and allows reconfigurable activation resolution. The proposed macro is fabricated in 65 nm and benchmarked on MNIST and CIFAR-10 datasets with accuracies of 98.67% and 89.85%, respectively, with energy-efficiency in the range of 15.4-138.6 TOPS/W.

KW - Compute-in-memory (CIM)

KW - convolutional neural network (CNN)

KW - delta-sigma

KW - static random access memory

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DO - 10.1109/LSSC.2023.3327213

M3 - Article

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SN - 2573-9603

VL - 6

SP - 293

EP - 296

JO - IEEE Solid-State Circuits Letters

JF - IEEE Solid-State Circuits Letters

ER -

SRAM In-Memory Computing Macro With Delta-Sigma Modulator-Based Variable-Resolution Activation

Abstract

Keywords

ASJC Scopus subject areas

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