Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture

Nishant S. Nukala, Niranjan Kulkarni, Sarma Vrudhula

Research output: Contribution to journalArticlepeer-review

7 Scopus citations


This paper describes a novel, first of its kind architecture for a threshold logic gate using conventional MOSFETs and an STT-MTJ (Spin Transfer Torque-Magnetic Tunneling Junction) device. The resulting cell, called STL which is extremely compact can be programmed to realize a large number of threshold functions, many of which would require a multilevel network of conventional CMOS logic gates. Next, we describe a novel array architecture consisting of STL cells onto which complex logic networks can be mapped. The resulting array, called STLA has several advantages not available with conventional logic. This type of logic (1) is non-volatile, (2) is structurally regular and operates like DRAM, (3) is fully observable and controllable, (4) has zero standby power. These advantages are demonstrated and compared by implementing a 16-bit carry look-ahead adder and a 32-bit Wallace tree multiplier in STLA and FPGA.

Original languageEnglish (US)
Pages (from-to)2452-2460
Number of pages9
JournalJournal of Parallel and Distributed Computing
Issue number6
StatePublished - Jun 2014


  • Gate array architecture
  • Low leakage magnetic circuits
  • Spin Transfer Torque-Magnetic Tunneling Junction (STT-MTJ)
  • Threshold logic

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence


Dive into the research topics of 'Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture'. Together they form a unique fingerprint.

Cite this