Metallization, and conductor systems in general, are a critical part of any VLSI chip, and as such can act to set limits on future down-scaling of such integrated circuits. Due to decreasing lateral and vertical dimensions, interconnections are rapidly becoming a problem in terms of device yield, reliability, signal delay time, and interdevice interactions. In this paper, we discuss how interconnection limitations will affect the scaling of advanced circuits. We also cover a number of issues regarding the interconnection technologies that will be required in future ULSI circuits. The problems with conductor systems begin with the interconnection topology which provides constraints and limitations. The physical problems then begin with the deposition of the materials. For example, chemical vapor deposition of metal or metal- silicide interconnects causes several unique concerns due to surface chemistry, leading to undesirable reactions and compositional and structural nonuniformities. Similarly, factors such as control of step coverage are important for reduced geometries. Recent experiments and modeling techniques which address these problems are therefore described. Lithographical aspects also pose problems in the scaling of metal lines and new pattern definition techniques are discussed. Finally, isolation of information within dense crossing interconnects can become very difficult, with coupling causing degradation of information within localized devices.