Abstract
A single-chip, 128-coefficient, asynchronous echo canceller has been developed. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate greater than 205 kHz.
Original language | English (US) |
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Title of host publication | Proceedings of the Annual IEEE International ASIC Conference and Exhibit |
Publisher | IEEE |
Pages | 181-184 |
Number of pages | 4 |
State | Published - 1995 |
Event | Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA Duration: Sep 18 1995 → Sep 22 1995 |
Other
Other | Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit |
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City | Austin, TX, USA |
Period | 9/18/95 → 9/22/95 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering