Simulation of void formation in interconnect lines

Alireza Sheikholeslami, Clemens Heitzinger, Helmut Puchner, Fuad Badrieh, Siegfried Selberherr

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations


The predictive simulation of the formation of voids in interconnect lines is important for improving capacitance and timing in current memory cells. The cells considered are used in wireless applications such as cell phones. pagers, radios, handheld games, and GPS systems. In backend processes for memory cells. ILD (interlayer dielectric) materials and processes result in void formation during gap fill. This approach lowers the overall k-value of a given metal layer and is economically advantageous. The effect of the voids on the overall capacitive load is tremendous. In order to simulate the shape and positions of the voids and thus the overall capacitance, the topography simulator ELSA (Enhanced Level Set Applications) has been developed which consists of three modules, a level set module, a radiosity module, and a surface reaction module. The deposition process considered is deposition of silicon nitride. Test structures of interconnect lines of memory cells were fabricated and several SEM images thereof were used to validate the corresponding simulations.

Original languageEnglish (US)
Title of host publicationProceedings of SPIE - The International Society for Optical Engineering
EditorsJ.F. Lopez, J.A. Montiel - Nelson, D. Pavlidis
Number of pages8
StatePublished - 2003
Externally publishedYes
EventVLSI Circuits and Systems - Maspalomas, Gran Canaria, Spain
Duration: May 19 2003May 21 2003


OtherVLSI Circuits and Systems
CityMaspalomas, Gran Canaria


  • Deposition
  • Interconnect lines
  • Level set method
  • Void formation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics


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