SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks

Gokul Krishnan, Sumit K. Mandal, Manvitha Pannala, Chaitali Chakrabarti, Jae Sun Seo, Umit Y. Ogras, Yu Cao

Research output: Contribution to journalArticlepeer-review

23 Scopus citations


In-memory computing (IMC) on a monolithic chip for deep learning faces dramatic challenges on area, yield, and on-chip interconnection cost due to the ever-increasing model sizes. 2.5D integration or chiplet-based architectures interconnect multiple small chips (i.e., chiplets) to form a large computing system, presenting a feasible solution beyond a monolithic IMC architecture to accelerate large deep learning models. This paper presents a new benchmarking simulator, SIAM, to evaluate the performance of chiplet-based IMC architectures and explore the potential of such a paradigm shift in IMC architecture design. SIAM integrates device, circuit, architecture, network-on-chip (NoC), network-on-package (NoP), and DRAM access models to realize an end-to-end system. SIAM is scalable in its support of a wide range of deep neural networks (DNNs), customizable to various network structures and configurations, and capable of efficient design space exploration. We demonstrate the flexibility, scalability, and simulation speed of SIAM by benchmarking different state-of-the-art DNNs with CIFAR-10, CIFAR-100, and ImageNet datasets. We further calibrate the simulation results with a published silicon result, SIMBA. The chiplet-based IMC architecture obtained through SIAM shows 130 and 72 improvement in energy-efficiency for ResNet-50 on the ImageNet dataset compared to Nvidia V100 and T4 GPUs.

Original languageEnglish (US)
Article number68
JournalACM Transactions on Embedded Computing Systems
Issue number5s
StatePublished - Oct 2021


  • Chiplet architecture
  • DNN acceleration
  • IMC benchmarking
  • in-memory compute
  • network-on-chip
  • network-on-package

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture


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