TY - JOUR
T1 - Semiconductor corner lot generation robust to process variation
T2 - Modeling and analysis
AU - Liu, Xiaonan
AU - Gough, Andrew M.
AU - Li, Jing
N1 - Funding Information:
This research was partly supported by NSF CMMI grants 1069246 and 1149602.
Publisher Copyright:
Copyright © 2018 “IISE”.
PY - 2018/2/1
Y1 - 2018/2/1
N2 - Product characterization is an important phase in developing new semiconductors. The goal is to determine if the new product will function when produced under the extreme edge of fabrication variation; if not, the product might be considered to have insufficient design margin, necessitating circuit redesign. Achieving this goal requires producing a so-called corner lot that consists of skew chips; i.e., chips whose key performance parameters that are expected to be around certain targeted extreme values. These skew chips are extensively tested to determine whether their functions still meet specifications. However, due to extensive variation in the fabrication process, few skewed chips can be guaranteed in a produced corner lot, and this is a long-standing frustration in the semiconductor industry. One approach to produce a satisfactory corner lot is through variation reduction of the fabrication process. Despite being a popular research area, variation reduction is a long-term effort that involves both technical and managerial considerations. We approach this problem from a different avenue by treating process variation as given and instead identifying a design strategy that guarantees production of a good corner lot robust to the variation. Specifically, we propose a first-of-its-kind rigorous mathematical formulation about this problem, investigate the theoretical properties and practical implications of this formulation, and further propose several optimal criteria and a corresponding design search algorithm. Applications to a broad range of semiconductor products are presented to demonstrate the universal improvement of the proposed optimal design compared with the traditional design used in current industrial practice.
AB - Product characterization is an important phase in developing new semiconductors. The goal is to determine if the new product will function when produced under the extreme edge of fabrication variation; if not, the product might be considered to have insufficient design margin, necessitating circuit redesign. Achieving this goal requires producing a so-called corner lot that consists of skew chips; i.e., chips whose key performance parameters that are expected to be around certain targeted extreme values. These skew chips are extensively tested to determine whether their functions still meet specifications. However, due to extensive variation in the fabrication process, few skewed chips can be guaranteed in a produced corner lot, and this is a long-standing frustration in the semiconductor industry. One approach to produce a satisfactory corner lot is through variation reduction of the fabrication process. Despite being a popular research area, variation reduction is a long-term effort that involves both technical and managerial considerations. We approach this problem from a different avenue by treating process variation as given and instead identifying a design strategy that guarantees production of a good corner lot robust to the variation. Specifically, we propose a first-of-its-kind rigorous mathematical formulation about this problem, investigate the theoretical properties and practical implications of this formulation, and further propose several optimal criteria and a corresponding design search algorithm. Applications to a broad range of semiconductor products are presented to demonstrate the universal improvement of the proposed optimal design compared with the traditional design used in current industrial practice.
KW - Semiconductor manufacturing
KW - product characterization
KW - variation reduction
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U2 - 10.1080/24725854.2017.1383636
DO - 10.1080/24725854.2017.1383636
M3 - Article
AN - SCOPUS:85035126040
SN - 2472-5854
VL - 50
SP - 126
EP - 139
JO - IISE Transactions
JF - IISE Transactions
IS - 2
ER -