Abstract
This paper presents a self-timed converter circuit which converts an n-digit redundant binary number to an (n + l)-bit binary number. Self-timed refers to the fact that the conversion is problem-dependent and requires variable conversion time to complete the operation. The propagation delay of the proposed converter circuit does not increase with the number of digits to be converted, but it is determined by the maximum number of consecutive O's in that number. This study shows that the statistical upper bound of the average maximum number of consecutive O's is log3n, or 3.78 for 64-digits. This implies that the proposed self-time circuit can be approximately 17 times faster than the ripple-type converter. Thus, the proposed converter is well-suited to high-speed, long-word digital arithmetic processors.
| Original language | English (US) |
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| Title of host publication | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors |
| Editors | Anon |
| Place of Publication | Piscataway, NJ, United States |
| Publisher | IEEE |
| Pages | 386-391 |
| Number of pages | 6 |
| State | Published - 1995 |
| Event | Proceedings of the 1995 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Austin, TX, USA Duration: Oct 2 1995 → Oct 4 1995 |
Other
| Other | Proceedings of the 1995 IEEE International Conference on Computer Design: VLSI in Computers & Processors |
|---|---|
| City | Austin, TX, USA |
| Period | 10/2/95 → 10/4/95 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering