Rigorous extraction of process variations for 65nm CMOS design

Wei Zhao, Yu Cao, Frank Liu, Kanak Agarwal, Dhruva Acharyya, Sani Nassif, Kevin Nowka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations


Statistical circuit analysis and optimization are critical for robust nanoscale design. To accurately perform such analysis, primary process variation sources need to be identified and modeled for further circuit simulation. In this work, we present a rigorous method to extract process variations from in-situ IV measurements. Transistor statistics are collected from a test chip fabricated in a 65nm SOI process. We recognize gate length (L), threshold voltage (Vth) and mobility (μ) as the leading variation sources, due to the tremendous process challenge in lithography, channel doping, and stress. To decompose them, only three IV points are needed from the leakage and linear regions. Both L and Vth variations are normally distributed, with negligible spatial correlation. By including extracted variations in the nominal model file, we can accurately predict the change of drive current in all process corners. The new extraction method guarantees excellent model matching with hardware for further statistical circuit analysis.

Original languageEnglish (US)
Title of host publicationESSDERC07 - 2007 37th European Solid State Device Research Conference
PublisherIEEE Computer Society
Number of pages4
ISBN (Print)1424411238, 9781424411238
StatePublished - 2007
EventESSDERC 2007 - 37th European Solid-State Device Research Conference - Munich, Germany
Duration: Sep 11 2007Sep 13 2007

Publication series

NameESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference


OtherESSDERC 2007 - 37th European Solid-State Device Research Conference

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials


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