Reverse-body biasing for radiation-hard by design logic gates

Different radiation hardening by design techniques for mitigating total ionizing dose (TID) effects in NMOS transistors are presented. NMOS annular layout transistors are compared to two-edge and hardened by reverse-body bias (RBB) with respect to CMOS gate area, delay, active and leakage power, and TID hardness. Accelerated testing using Co-60 irradiation of test structures on a 130 nm bulk CMOS process shows that RBB provides smaller devices and allows less chip-level leakage at 1 Mrad(Si) than a design hardened using annular gates has pre-irradiation. Simulations of fanout-of-four (F04) two-input NAND gates show that RBB provides an energy-delay product (EDP) comparable to conventional two-edge gates. Different annular topologies have EDP 35% to over 350% greater.