Quadtree layout

Sourav Bhattacharya, Shekar Kirani, Wei Tek Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Quadtree data structure has been used in a number of applications. However, VLSI embedding of quadtree based parallel architecture using grid model has not been studied. This paper studies VLSI embedding of quadtree using grid model. H-tree layout for binary tree is extended for trivial quadtree layout, followed by developing two layout strategies for rectangular grids. Then, two generic layout styles (standard layout and X-layout) are proposed for higher order grids (e.g., hexagonal and octagonal grids). Base tile layout patterns are proposed for area compaction with recursive X-layout. In each case, layout dimensions and I/O bandwidth are computed. We demonstrate how the two generic layouts can be mixed to obtain higher I/O bandwidth and estimate the area sacrifice. An improved recursive layout mixing strategy is proposed.

Original languageEnglish (US)
Title of host publicationProc Second Great Lakes Symp VLSI
Place of PublicationLos Alamitos, CA, United States
PublisherPubl by IEEE
Number of pages8
StatePublished - 1991
Externally publishedYes
EventProceedings of the Second Great Lakes Symposium on VLSI - Kalamazoo, MI, USA
Duration: Feb 28 1992Feb 29 1992


OtherProceedings of the Second Great Lakes Symposium on VLSI
CityKalamazoo, MI, USA

ASJC Scopus subject areas

  • Engineering(all)


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