Proposing a Solution for Single-Event Upset in 1T1R RRAM Memory Arrays

Amr M.S. Tosson, Shimeng Yu, Mohab H. Anis, Lan Wei

Research output: Contribution to journalArticlepeer-review

5 Scopus citations


Resistive random access memory (RRAM) is a promising emerging technology to provide nonvolatile and scalable data storage in advanced technologies. As a noncharge-based device, the intrinsic RRAM device is immune to single-event effects. However, single-event upset (SEU) due to the MOSFET in the one-transistor-one-RRAM (1T1R) array can be observed. A novel methodology, which can be easily integrated to the other memory system components, is proposed in this paper to detect and correct SEU in 1T1R RRAM memory array. Using the HfOx 1T1R RRAM array as an example, our simulation results show that, for an 8-Gb memory array, the proposed technique can detect and fix the soft errors induced by the heavy ion strikes with 0.66% increase in the chip area. Also, the suggested methodology minimally increases the energy consumption of the read and write operations by 0.2% and 0.1%, respectively.

Original languageEnglish (US)
Pages (from-to)1239-1247
Number of pages9
JournalIEEE Transactions on Nuclear Science
Issue number6
StatePublished - Jun 2018


  • Heavy ions
  • nonvolatile memory
  • resistive random access memory (RRAM) one-transistor-one-RRAM (1T1R) array
  • single-event upset (SEU)
  • soft errors

ASJC Scopus subject areas

  • Nuclear and High Energy Physics
  • Nuclear Energy and Engineering
  • Electrical and Electronic Engineering


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