Programmable processor for cryptography

Sukumar S. Raghuram, Chaitali Chakrabarti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations


Cryptography has numerous applications in today's world, the most prevalent one being transferring messages safely over the network. Cryptographic algorithms are either implemented in software on a general-purpose processor or in hardware on an application-specific processor. While the software implementations tend to be time consuming, the hardware implementations are too specific and cannot even support small modifications. In this paper, a programmable architecture that can handle a large number of algorithms including DES, RSA, Blowfish, SAFER, et cetera has been developed. The architecture consists of addition, subtraction, modular multiplication, exponentiation and XOR units and thus can support a majority of the cryptographic algorithms. A high data rate is achieved by applying loop unrolling to the Montgomery algorithm that is used for modular multiplication and exponentiation. The differences in the number of bits, key length, and sequence of operations is handled by the microprogrammed control unit. A VHDL model has been developed and synthesized using AutoLogic II from Mentor Graphics. The results show a frequency of operation of 77 Megahertz and an area of 23,000 `Optimization COST' units.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - 2000
EventProceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems - Geneva, Switz
Duration: May 28 2000May 31 2000


OtherProceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems
CityGeneva, Switz

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials


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