TY - JOUR
T1 - Process scalability of pulse-based circuits for analog image convolution
AU - D'Angelo, Robert
AU - Du, Xiaocong
AU - Salthouse, Christopher D.
AU - Hollosi, Brent
AU - Freifeld, Geremy
AU - Uy, Wes
AU - Huang, Haiyao
AU - Tran, Nhut
AU - Chery, Armand
AU - Seo, Jae-sun
AU - Cao, Yu
AU - Poppe, Dorothy C.
AU - Sonkusale, Sameer R.
N1 - Funding Information:
Manuscript received October 13, 2017; revised January 10, 2018 and February 26, 2018; accepted March 15, 2018. Date of publication April 19, 2018; date of current version August 3, 2018. This work was supported by the Charles Stark Draper Laboratory, Cambridge, MA, USA, in collaboration with Tufts University and Arizona State University. This paper was recommended by Associate Editor G. J. Dolecek. (Corresponding author: Sameer R. Sonkusale.) R. D’Angelo, C. D. Salthouse, B. Hollosi, G. Freifeld, W. Uy, H. Huang, N. Tran, A. Chery, and D. C. Poppe are with the Charles Stark Draper Laboratory, Cambridge, MA 02139 USA.
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2018/9
Y1 - 2018/9
N2 - This paper studies the process scalability of pulse-mode CMOS circuits for analog 2-D convolution in computer vision systems. A simple, scalable architecture for an integrate and fire neuron is presented for implementing weighted addition of pulse-frequency modulated (PFM) signals. Sources of error are discussed and modeled in a detailed behavioral simulation and compared with equivalent transistor-level simulations. Next, the design of a 180-nm PFM chip with programmable weights is presented, and full image convolutions are demonstrated with the analog hardware. Preliminary chip measurements for a 45-nm implementation are also included to demonstrate process scalability. Design considerations for porting this architecture to nanometer processes, including FinFET technologies, are then discussed. This paper concludes with a simulation study on scaling down to 10 nm using a predictive technology model.
AB - This paper studies the process scalability of pulse-mode CMOS circuits for analog 2-D convolution in computer vision systems. A simple, scalable architecture for an integrate and fire neuron is presented for implementing weighted addition of pulse-frequency modulated (PFM) signals. Sources of error are discussed and modeled in a detailed behavioral simulation and compared with equivalent transistor-level simulations. Next, the design of a 180-nm PFM chip with programmable weights is presented, and full image convolutions are demonstrated with the analog hardware. Preliminary chip measurements for a 45-nm implementation are also included to demonstrate process scalability. Design considerations for porting this architecture to nanometer processes, including FinFET technologies, are then discussed. This paper concludes with a simulation study on scaling down to 10 nm using a predictive technology model.
KW - Time-mode circuits
KW - convolution
KW - neuromorphic circuits
KW - spiking neurons
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U2 - 10.1109/TCSI.2018.2821691
DO - 10.1109/TCSI.2018.2821691
M3 - Article
AN - SCOPUS:85045741712
SN - 1549-8328
VL - 65
SP - 2929
EP - 2938
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 9
M1 - 8341826
ER -